section 1.cyclone FPGA Family data sheet的翻译

This section provides designers with the data sheet specifications for Cyclone®devices. The chapters contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information,DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Cyclone devices.

这一部分为设计者介绍了cyclone器件家族的特性。本章包含内部结构信息、配置、JTAG边界扫描测试信息、DC工作条件、AC时序特点、功耗指南和cyclone器件的订阅信息。

chapter1 Introduction

The Cyclone®field programmable gate array family is based on a 1.5-V,0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial confi