I2C接口的KSZ9897 Switch

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已于 2024-04-03 17:39:01 修改

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分类专栏： NXP iMx8mm 文章标签： KSZ9897 I2C phy-mode RGMII

于 2020-09-19 15:28:28 首次发布

本文链接：https://blog.csdn.net/suiyuan19840208/article/details/108680414

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1： I2C配置接口的9897 DTS

/*
imx8mm 中AR8031的默认DTS的配置，与PHY的配置接口为：MDIO
&fec1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fec1>;
        phy-mode = "rgmii-id";
        phy-handle = <&ethphy0>;
        fsl,magic-packet;
        status = "okay";
        mdio {
	        #address-cells = <1>;
	        #size-cells = <0>;

	        ethphy0: ethernet-phy@0 {
	                compatible = "ethernet-phy-ieee802.3-c22";
	                reg = <0>;
	                at803x,led-act-blind-workaround;
	                at803x,eee-okay;
	                at803x,vddio-1p8v;
	        };
        };
};
phy-mode = "rgmii-txid";
*/
&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	fsl,magic-packet;
	status = "okay";
	phy-mode = "rgmii-txid";
  fixed-link {
    speed = <1000>;
    full-duplex;
  };
};

I2C非MDIO配置方式的KSZ9897 Switch DTS配置。

 i2c_ksz9897: ksz9897@5f {
	compatible = "microchip,ksz9897";
	reg = <0x5f>;
	phy-mode = "rgmii-txid";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ksz9897_irq>;
	interrupt-parent = <&gpio1>;
	interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
	status = "okay";
	ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				label = "lan1";
			};
			port@1 {
				reg = <1>;
				label = "lan2";
			};
			port@2 {
				reg = <2>;
				label = "lan3";
			};
			port@3 {
				reg = <3>;
				label = "lan4";
			};
			port@4 {
				reg = <4>;
				label = "lan5";
			};
			port@5 {
				reg = <5>;
				label = "cpu";
				ethernet = <&fec1>;
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
			port@6 {
				reg = <6>;
				label = "lan6";
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
	 };
 };

2: phy-mode = "rgmii-txid";的解析

DTS中的任何配置，驱动程序中都会对其进行解析。看代码，找代码，根据代码来确认不同配置的的处理逻辑或流程。

int of_get_phy_mode(struct device_node *np)
{
	const char *pm;
	int err, i;

	err = of_property_read_string(np, "phy-mode", &pm);
	if (err < 0)
		err = of_property_read_string(np, "phy-connection-type", &pm);
	if (err < 0)
		
		return err;
	printk("%s %s %d,pm:%d\n",__FILE__,__FUNCTION__,__LINE__,pm);

	for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++)
		if (!strcasecmp(pm, phy_modes(i)))
			return i;

	return -ENODEV;
}
/* Interface Mode definitions */
typedef enum {
	PHY_INTERFACE_MODE_NA,            //0
	PHY_INTERFACE_MODE_INTERNAL,      //1
	PHY_INTERFACE_MODE_MII,
	PHY_INTERFACE_MODE_GMII,
	PHY_INTERFACE_MODE_SGMII,
	PHY_INTERFACE_MODE_TBI,
	PHY_INTERFACE_MODE_REVMII,
	PHY_INTERFACE_MODE_RMII,
	PHY_INTERFACE_MODE_RGMII,         //8
	PHY_INTERFACE_MODE_RGMII_ID,
	PHY_INTERFACE_MODE_RGMII_RXID,   //10
	PHY_INTERFACE_MODE_RGMII_TXID,
	PHY_INTERFACE_MODE_RTBI,
	PHY_INTERFACE_MODE_SMII,
	PHY_INTERFACE_MODE_XGMII,
	PHY_INTERFACE_MODE_MOCA,
	PHY_INTERFACE_MODE_QSGMII,
	PHY_INTERFACE_MODE_TRGMII,
	PHY_INTERFACE_MODE_1000BASEX,
	PHY_INTERFACE_MODE_2500BASEX,
	PHY_INTERFACE_MODE_RXAUI,
	PHY_INTERFACE_MODE_XAUI,
	/* 10GBASE-KR, XFI, SFI - single lane 10G Serdes */
	PHY_INTERFACE_MODE_10GKR,
	PHY_INTERFACE_MODE_MAX,
} phy_interface_t;
这是写MAC层进行初始化时，根据硬件定义来进行配置的。

3：XMII Port Control 1 Register 寄存器

我这边在移植驱动之后，网络可以进行数据接收而不能成功发送：是由于上面bit4寄存器配置的问题造成，将默认值从0 更改为1

请注意：.下面是错误的情况，正确为：phy-mode = "rgmii-txid"; 错误为：phy-mode = "rgmii-rxid";

static phy_interface_t to_phy_interface(const char *phy_connection_type)
{
	if (strcasecmp(phy_connection_type, "mii") == 0)
		return PHY_INTERFACE_MODE_MII;
	if (strcasecmp(phy_connection_type, "gmii") == 0)
		return PHY_INTERFACE_MODE_GMII;
	if (strcasecmp(phy_connection_type, "tbi") == 0)
		return PHY_INTERFACE_MODE_TBI;
	if (strcasecmp(phy_connection_type, "rmii") == 0)
		return PHY_INTERFACE_MODE_RMII;
	if (strcasecmp(phy_connection_type, "rgmii") == 0)
		return PHY_INTERFACE_MODE_RGMII;
	if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
		return PHY_INTERFACE_MODE_RGMII_ID;
	if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
		return PHY_INTERFACE_MODE_RGMII_TXID;
	if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
		return PHY_INTERFACE_MODE_RGMII_RXID;
	if (strcasecmp(phy_connection_type, "rtbi") == 0)
		return PHY_INTERFACE_MODE_RTBI;
	if (strcasecmp(phy_connection_type, "sgmii") == 0)
		return PHY_INTERFACE_MODE_SGMII;

	return PHY_INTERFACE_MODE_MII;
}
DTS中的不同配置：phy-mode = "rgmii-txid"; 通过上面的解析得到的phy interface的值不同。

[    0.776039] ksz9897 2-005f: chip id 0x00989700
[    0.779511] random: fast init done
[    0.783935] -
[    0.783949] 98 97
[    0.783949] avb=0  rr=0  giga=1
[    0.783949]  compatible: ksz9897
[    0.783949] ports: 7f
[    0.783949] features: 2a0000 m:-1 a:0 s:ffffffff
[    0.783949] ports: 7f
[    0.783949] 0= 5:20 1:01 6; 0:40 0
[    0.783949] 1= 0:01 2:02 1; 1:01 0
[    0.783949] 2= 1:02 3:04 2; 2:02 0
[    0.783949] 3= 2:04 4:08 3; 3:04 0
[    0.783949] 4= 3:08 5:10 4; 4:08 0
[    0.783949] 5= 4:10 0:40 5; 5:10 0
[    0.783949] 6= 6:40 6:20 7; 6:20 1
[    0.783949] mask: 7f 20 7f
[    0.783949] mask: 20 7f; 400 200
[    0.783949] port: 7 6 5
[    0.936529] host: 5 11
[    0.936529] xmii: 7808 78 08; 1000 2
[    1.020480] libphy: Switch MII bus: probed
[    1.044647] jtag: 100c 74cd
[    1.044647] 1140 0189 7996 ced0 0020 0000
[    1.044647] xmii: f808 f8 08; 1000 2
[    1.044647]  sw_init_phy_priv 0=p:0; f:1 c:6 i:6
[    1.044647]  sw_init_phy_priv 1=p:0; f:1 c:1 i:6
[    1.044647]  sw_init_phy_priv 2=p:1; f:2 c:1 i:1
[    1.044647]  sw_init_phy_priv 3=p:2; f:3 c:1 i:2
[    1.044647]  sw_init_phy_priv 4=p:3; f:4 c:1 i:3
[    1.044647]  sw_init_phy_priv 5=p:4; f:5 c:1 i:4
[    1.044647]  sw_init_phy_priv 6=p:6; f:6 c:1 i:7
[    1.044647]  sw_init_phy_priv 7=p:5; f:7 c:1 i:5
[    6.510096] sw_set_global_ctrl,interface=11,HOST_PORT:5,phy_port_cnt:5
[    6.510096] sw_set_global_ctrl,interface=11,HOST_PORT:5,phy_port_cnt:5,data:8
[    6.510096] cached: 7808
[    6.627599] eee txq wait: 000a
[    8.058535] random: crng init done
[    8.921622]   sgmii_setup 0 1 1
[    8.921622]   cfg: 0004
[    8.921622] CFG: 0019
[    9.030724]   adv: 0020
[    9.030724] ADV: 01a0
[    9.030724] AUTO_NEG: 1340
[    9.972125] status 00000000
[    9.972125] states 00000000
[   10.080238] result 00000000
[   10.080238]  fewer: 0 0


==============================FEC PHY 关键的信息========================================

Microchip KSZ9897 Switch sw.0:00: attached PHY driver [Microchip KSZ9897 Switch] (mii_bus:phy_addr=sw.0:00, irq=70)

[   14.375068] libphy: fec_enet_mii_bus: probed
[   14.382811] 0=advertised: 07000DE1-07000DE1; partner: 00000000-00000000; link: 0000-4000
[   14.432196] 1=advertised: 07000DE1-07000DE1; partner: 00000000-00000000; link: 0000-4000
[   14.500395] FTR:drivers/net/ethernet/freescale/fec_main.c fec_enet_clk_enable 2540,enable:0 
[   14.509310] fec 30be0000.ethernet eth0: registered PHC device 0
[   14.514221] 2=advertised: 07000DE1-07000DE1; partner: 00000000-00000000; link: 0000-4000
[   14.528903] 3=advertised: 07000DE1-07000DE1; partner: 00000000-00000000; link: 0000-4000
[   14.542587] 4=advertised: 07000DE1-07000DE1; partner: 00000000-00000000; link: 0000-4000

4：寄存器读写

其中 2表示：第二组I2C总线，0x5f表示总线下特定设备的地址(KSZ9897在总线上的地址，已经固定为：0x5F)，W2表示读，W3表示写
0x63 0x01:表示寄存器的地址
w3时：写入寄存器的值
w2时：跟驱动的字节数,r4表示读4个字节，R1表示读一个字节。
i2ctransfer -f -y 2 w3@0x5f 0x63 0x01 0x1c  
i2ctransfer -f -y 2 w2@0x5f 0x63 0x01 r4   
root@imx8mmevk:~# i2ctransfer -f -y 2 w2@0x5f 0x00 0x01 r1
0x98
root@imx8mmevk:~# i2ctransfer -f -y 2 w2@0x5f 0x00 0x01 r2
0x98 0x97
root@imx8mmevk:~# i2ctransfer -f -y 2 w2@0x5f 0x00 0x01 r10
0x98 0x97 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
root@imx8mmevk:~# i2ctransfer -f -y 2 w2@0x5f 0x00 0x00 r1 
0x00
root@imx8mmevk:~# i2ctransfer -f -y 2 w2@0x5f 0x00 0x00 r2
0x00 0x98
root@imx8mmevk:~# i2ctransfer -f -y 2 w2@0x5f 0x00 0x01 r1 
0x98
root@imx8mmevk:~# i2ctransfer -f -y 2 w2@0x5f 0x00 0x02 r1 
0x97
root@imx8mmevk:~# i2ctransfer -f -y 2 w2@0x5f 0x00 0x06 r1  
0x00
root@imx8mmevk:~# i2ctransfer -f -y 2 w2@0x5f 0x00 0x06 r2
0x00 0x00
root@imx8mmevk:~# i2ctransfer -f -y 2 w2@0x5f 0x01 0x04 r4

下面是100的配置

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I2C接口的KSZ9897 Switch

1： I2C配置接口的9897 DTS/*imx8mm 中AR8031的默认DTS的配置，与PHY的配置接口为：MDIO&fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <&ethphy0>; fsl,magic-packe
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