2 Comparator Block
The comparator module described in this reference guide is a true analog voltage comparator in the VDDA domain. The analog portion of the block include the comparator, its inputs and outputs, and the internal DAC reference. The digital circuits, referred to as the wrapper in this document, include the DAC controls, interface to other on-chip logic, output qualification block, and the control signals.
2.比较器模块
在这个参考指南中所描述的比较器模块是VDDA域中一个真正的模拟电压比较器。模拟块的一部分包含比较器,输入和输出,以及内部的DAC参考基准。数字电路在本文档当中被称为程序轮询,包括DAC控制,其他片上逻辑的接口,输出限定单元和控制信号。
2.1 Features
The comparator block (see Figure 39) can accommodate two external analog inputs or one external analog input using the internal DAC reference for the other input. The output of the comparator can be passed asynchronously or qualified and synchronized to the system clock period. The comparator output is routed to both the ePWM Trip Zone modules, as well as the GPIO output multiplexer.
2.1 特性
比较器模块(见图39)可以提供两个外部模拟输入或者一个外部模拟输入,其中另一个输入使用内部的DAC参考基准。比较器的输出异步传输,或者被限定成与系统时钟周期同步。比较器的输出被路由到ePWM TZ
模块,也可以路由到GPIO输出多路复用器。
2.2 Comparator Function
The comparator in each comparator block is an analog comparator module, and as such its output is asynchronous to the system clock. The truth table for the comparator is shown in Table 24.
2.2比较器功能
每一个比较器模块中的比较器都是一个模拟比较器模块,就其本身而言,其输出与系统时钟是异步的。比较器的真值表如表24所示。
There is no definition for the condition Voltage A = Voltage B since there is hysteresis in the response of the comparator output. Refer to the device datasheet for the value of this hysteresis. This also limits the sensitivity of the comparator output to noise on the input voltages. The output state of the comparator, after qualification, is reflected by the COMPSTS bit in the COMPSTS register. Since this bit is part of the wrapper, clocks must be enabled to the comparator block for the COMPSTS bit to actively show the comparator state.
上面没有对Voltage A = Voltage B的条件进行定义,因为比较器的输出响应有滞后。滞后的值请参阅器件的数据手册。比较器输出灵敏度将受输入电压上的噪声限值。经过限定后,比较器输出的状态受COMPSTS寄存器中COMPSTS位的影响。因为这个位是轮询程序的一部分,为了COMPSTS位主动的显示比较器的状态,所以比较器模块的时钟必须使能。
Default state 缺省状态
Round—robin 循环的
Raw 原始的