module auto_sale(clk,rst_n,in,out,out_val);
input[1:0] in;
input clk,rst_n;
output reg[1:0] out;
output reg out_val;
reg[3:0] state;
reg[3:0] state_next;
localparam S0=4'b0000;
localparam S1=4'b0001;
localparam S2=4'b0010;
localparam S3=4'b0100;
localparam S4=4'b1000;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
begin
state <= S0;
end
else begin
state <= state_next;
end
end
always @(*) begin
case(state)
S0:
if(in==2'b01)
state_next =S1;
else if(in==2'b10)
state_next = S2;
else state_next = state;
S1:
if(in==2'b01)
state_next = S2;
else if(in ==2'b10)
state_next =S3;
else
state_next = state;
S2:
if(in==2'b01)
state_next = S3;
else if(in==2'b10)
state_next = S4;
else
state_next =state;
S3:
if(in==2'b01)
state_next= S4;
else if (in ==2'b10)
state_next= S4;
else state_next = state;
S4:
if(in==2'b01)
state_next = S1;
else if(in==2'b10)
state_next = S2;
else state_next = state;
default: state = S0;
endcase
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
out <=0;
else if ((state==S3&&in!=2'b00) ||(state==S2&&in == 2'b10))
out<=1;
else
out<=0;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
out_val <=0;
else if(state ==S3&&in==2'b10)
out_val <=1;
else
out_val <=0;
end
endmodule