arm-trusted-firmware 收到psci的smc处理的过程

tiantao2012

已于 2024-09-03 11:42:12 修改

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分类专栏： arm-trusted-firmware 文章标签： arm开发

于 2017-05-22 09:20:41 首次发布

本文链接：https://blog.csdn.net/tiantao2012/article/details/72621155

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当kernel psci 通过smc陷到el3时的入口函数如下：
arm-trusted-firmware-master/bl31/aarch64/runtime_exceptions.S
vector_entry sync_exception_aarch64
   /*
   * This exception vector will be the entry point for SMCs and traps
   * that are unhandled at lower ELs most commonly. SP_EL3 should point
   * to a valid cpu context where the general purpose and system register
   * state can be saved.
   */
   handle_sync_exception
   check_vector_size sync_exception_aarch64
在handle_sync_exception中判断是smc_handler64还是smc_handler32
.macro   handle_sync_exception
   /* Enable the SError interrupt */
   msr   daifclr, #DAIF_ABT_BIT

   str   x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]

#if ENABLE_RUNTIME_INSTRUMENTATION
   /*
   * Read the timestamp value and store it in per-cpu data. The value
   * will be extracted from per-cpu data by the C level SMC handler and
   * saved to the PMF timestamp region.
   */
   mrs   x30, cntpct_el0
   str   x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
   mrs   x29, tpidr_el3
   str   x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
   ldr   x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
#endif

   mrs   x30, esr_el3
   ubfx   x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH

   /* Handle SMC exceptions separately from other synchronous exceptions */
   cmp   x30, #EC_AARCH32_SMC
   b.eq   smc_handler32

   cmp   x30, #EC_AARCH64_SMC
   b.eq   smc_handler64

   /* Other kinds of synchronous exceptions are not handled */
   no_ret   report_unhandled_exception
   .endm
我们这里以smc_handler32为例
smc_handler64:
   /*
   * Populate the parameters for the SMC handler.
   * We already have x0-x4 in place. x5 will point to a cookie (not used
   * now). x6 will point to the context structure (SP_EL3) and x7 will
   * contain flags we need to pass to the handler Hence save x5-x7.
   *
   * Note: x4 only needs to be preserved for AArch32 callers but we do it
   *       for AArch64 callers as well for convenience
   */
   stp   x4, x5, [sp, #CTX_GPREGS_OFFSE