ECE5882/6882 SPSS

Java Python Assignment

ECE5882/6882

Part 1:4 pts.

RS = 50Ω and ZL = 72+j94Ω.

In the above circuit, a matching network (MN) is used to match the load impedance ZL with the source resistor RS. The input signal frequency is 500 MHz.

[a] 1 pts. Design a Matching (MN) Circuit using Smith Chart.

[b] 1 pts. Draw complete circuit schematic, including the load.

[c] 1 pts. Simulate the complete circuit and plot the ratio of the voltage at the output to the input voltage from 0 to 1.5 GHz (vout/vin vs f ). Report bandwidth-BW and Quality factor.

[d] 1 pts Find the power efficiency delivered to the load with and without the matching network. You can sue simulation for this.

Part 2: 6 pts.

Let IC1= 2-10 mA, VT = 26 mV, Rs =50 ohm. Vb1  & Vb2 are the bias voltages.

[a] 1 pts. Find an equation for H(w)= vout(w)/vin(w). Use the high frequency model for the transistors. Note Q1 and Q2 are the same transistors.

[b] 1 pts. Present an expre ECE5882/6882 AssignmentSPSS ssion for the low-frequency voltage gain, Av = vout/vin.

[c] 2 pts. Design and simulate this amplifier such that the gain will be equal or more than 10 dB, at 100MHz or higher (fopt ≥100 MHz). Clearly show the biasing circuits used to obtain Vb1 and Vb2 .

[d] 1 pts. Use AC analysis, plot the gain (vout/vin). Discuss low-frequency and high frequency gains by considering several points at low frequencies as well high frequencies for comparison. Make reasonable arguments.

[e] 1 pts. Analyse the linearity of the amplifier by plotting 1dB compression point.

[f] Bonus: 1 pts. If you plot and calculate IIP3 power (PIIP3).

Note: An ideal transistor is not accepted.

Submission:

Submit your report via the link provided on the Moodle before 4:30 pm, September 3.

•   You are required to submit your circuit (only schematic file, LTspice or ADS is fine).

•   This assignment should be done individually