VITA 57 FPGA 夹层卡（FMC）

来自： https://fmchub.github.io/appendix/VITA57_FMC_HPC_LPC_SIGNALS_AND_PINOUT.html

High-pin count (HPC) connector, HPC pinout

HPC 连接器有 10 排（A、B、C、D、E、F、G、H、J、K），每排 40 针。 下表总结了 HPC 连接器的引脚。

HPC连接器引脚总结：

General pin function	Pin count
Gigabit data	40
Gigabit clocks	4
User data	160
User clocks	8
I2C	2
JTAG	5
State flags	5
Power supply	15
Ground	159
Reserved	2
Footprints可以在 Lib_Altium github库中查看。

Low-pin count (LPC) connector, LPC pinout

LPC 连接器有 4 排（C、D、G、H），每排 40 针。 下表总结了 LPC 连接器的引脚。

LPC连接器引脚总结：

General pin function	Pin count
Gigabit data	4
Gigabit clocks	4
User data	68
User clocks	4
I2C	2
JTAG	5
State flags	4
Power supply	10
Ground	61
Footprints可以在 Lib_Altium github库中查看。

Pin and signal description

Pin Name	description
LA[00…33]_P	LA_XX - LPC, FPGA Bank A
LA[00…33]_N	68 user-defined, single-ended signals or 34 user-defined, differential pairs (mandatory for LPC)
HA[00…23]_P	HA_XX - HPC, FPGA Bank A
HA[00…23]_N	48 user-defined, single-ended signals or 24 user-defined, differential pairs
HB[00…21]_P,	HB_XX - HPC, FPGA Bank B
HB[00…21]_N	44 user-defined, single-ended signals or 22 user-defined, differential pairs
XX_P_CC
XX_N_CC	User-defined clock capable (CC) pins. These pins can be used for clock signals.
CLK[0…3]_M2C_P
CLK[0…3]_M2C_N	4 user clock, differential pairs (CLK[2…3]_M2C only for HPC), bidrectional
GBTCLK[0…1]_M2C_P
GBTCLK[0…1]_M2C_N	Clock signals for multi-gigabit transceiver data pairs (GBTCLK1_x only for HPC)
DP[0…9]_M2C_P
DP[0…9]_M2C_N	multi-gigabit transceiver data pairs (one is mandatory for LPC, 10 in total with HPC)
DP[0…9]_C2M_P
DP[0…9]_C2M_N	multi-gigabit transceiver data pairs (one is mandatory for LPC, 10 in total with HPC)
GA[0…1]	Geographical address of the module (can be used for adressing on I2C bus). These pins are driven by the carrier card.
VREF_A_M2C	Reference voltage for signaling standard of bank A (LAxx and HAxx). Can be left floating, if not required.
VREF_B_M2C	Reference voltage for signaling standard of bank B (HBxx). Can be left floating, if not required.
VIO_B_M2C	This voltage is sourced by the mezzanine module which supports the HB bus. It is used to power the IO Bank of the FPGA.
3P3VAUX	3.3 V auxiliary power supply (max. 20 mA, max. 150 uF cap. load).
VADJ	Adjustable voltage level (0 … 3.3 V) from the carrier to the mezzanine card (max. 4 A, max. 1000 uF cap. load).
3P3V	3.3 V power from the carrier to the mezzanine card (max. 3 A, max. 1000 uF cap. load).
12P0V	12 V power from the carrier to the mezzanine card (max. 1 A, max. 1000 uF cap. load).
TRST_L	JTAG Reset
TCK	JTAG Clock
TMS	JTAG Mode Select
TDI	JTAG Data In, if JTAG chain is not used by mezzanine card, short TDI and TDO.
TDO	JTAG Data Out, if JTAG chain is not used by mezzanine card, short TDI and TDO.
PRSNT_M2C_L	Present signal. Indicates that a mezzanine module is attached to the carrier. Low active (tie to GND on FMC)
PG_C2M	Active high power good signal. High indicates that VADJ, 12P0V, and 3P3V are within tolerance.
PG_M2C	Active high power good signal. High indicates that VIO_B_M2C, VREF_A_M2C, and VREF_B_M2C are within tolerance.
SCL	I2C serial clock. Interface can support Intelligent Platform Management Interface (IPMI) commands.
SDA	I2C serial data. Interface can support Intelligent Platform Management Interface (IPMI) commands.
RES[0…1]	Reserved, left floating
GND	Signal ground
M2C	Mezzanine-to-Carrier, signal is driven by the mezzanine module and received by the carrier card
C2M	Carrier-to-Mezzanine, signal is driven by the carrier card and received by the mezzanine module

FMC互连

VITA 标准规定了 VITA 57.4 FPGA Mezzanine Card Plus (FMC+) 连接器和 VITA 57.1 FPGA Mezzanine Card (FMC) 连接器的配置：
FMC+ (VITA 57.4)

• High Serial Pin Connector (HSPC) with 560 pins (provides 24 GT interfaces)
• High Serial Pin Connector extension (HSPCe) with 80 pins (provides additional 8 GT interfaces; this connector is optional)
  
• High Pin Count (HPC) 400 I/O high-speed array system
• Mechanically compatible Low Pin Count (LPC) 160 I/O can also be used with any of the form factors detailed in the standard
  

Reference

1. ANSI/VITA 57.1-2008
2. Overview of VITA57 – FMC, Curtiss Wright, www.vita.com/Resources/Learn/FMC%20Overview.pptx
3. KC705 Evaluation Board for the Kintex-7 FPGA, Xilinx UG810
4. I/O Design Flexibility with the FPGA Mezzanine Card (FMC), Xilinx WP315
5. FMCHUB - FPGA MEZZANINE CARDs
6. Lib_Altium, Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
7. FMC LPC Breakout board, Datasheet of Open-source hardware FMC module