- 博客(1)
- 资源 (11)
- 收藏
- 关注
原创 xilinx FIFO
1、FIFO复位问题 摘自《FIFO Generator v9.3 PG057 December 18, 2012 》P126
2018-11-27 11:09:26 1626
xapp1249-smpte-sdi-interfaces-7series-gtx-transceivers
文档包括英文原版与中文翻译,中文翻译为机器翻译,质量很差,可以对照原文进行参考,本文是使用xilinx7 系列 GTX 收发器 进行12G SDI收发
2019-05-16
TB-FMCH-DP3 Hardware User’s Manual
The TB-FMCH-DP3 provides test environment for DisplayPort Standard Version1, Revision 2a.
It supports below features
4 Lane of 1.62Gbps, 2.7Gbps and 5.4Gbps
It uses TI SN75SP130 for Source(TX) and SN65DP159 for Sink(RX)
AUX Communication.(FAUX is not supported)
2019-05-14
TB-FMCH-12GSDI Hardware User Manual
The TB-FMCH-12GSDI FMC has a dedicated SDI input, a dedicated SDI output, and three SDI
channels that are either input or output. Each SDI channel supports a data rate up to 11.88 Gbps. It
also has a video sync input for a video sync separator chip. All video signal connections are via 75
ohm HDBNC jacks. A video clock generator can also produce common video timing signals from
oscillators or from HVF sync signals from the host FPGA.
2019-05-14
DP1.4标准——VESA Proposed DisplayPort (DP) Standard
本文档包括2015年发布的:《DP1.4标准(VESA Proposed DisplayPort (DP) Standard》866页,《DisplayPort和eDP物理层兼容性测试》,DisplayPort1.1-1.2-1.3-区别简介
2018-10-12
DDR3 Demo for the Lattice ECP3 Versa Evaluation Board Users Guide
Lattice ECP3 芯片配置DDR3 Demo f
2017-08-22
DP 连接器规格VESA标准
This document describes the requirements for self-testing of connector products
that incorporate the DisplayPort™ interface to bear the “DP Certified” Logo.
2017-08-16
空空如也
TA创建的收藏夹 TA关注的收藏夹
TA关注的人