hdlbits.01xz.net /Circuits/Sequential Logic/Finite State Machines/Simple FSM 3(synchronous reset)

Tezt777

于 2023-01-24 10:44:09 发布

阅读量58

点赞数

分类专栏： FPGA 文章标签： fpga开发 Powered by 金山文档

本文链接：https://blog.csdn.net/u011493332/article/details/128755604

版权

FPGA 专栏收录该内容

53 篇文章 0 订阅

订阅专栏

该Verilog代码定义了一个顶层数字模块，包含一个同步复位的状态机。状态机有四个状态A、B、C和D，根据输入in在这些状态之间转换。当reset信号有效时，状态机重置为状态A。输出out在状态D时为1，其他状态为0。

摘要由CSDN通过智能技术生成

就是把上一个里面对reset边沿的判断挪到 always@(*)里面处理

module top_module(
    input clk,
    input in,
    input reset,
    output out); //
    
    reg [3:0] state, next_state;
    parameter A = 4'b0001;
    parameter B = 4'b0010;
    parameter C = 4'b0100;
    parameter D = 4'b1000;
    
    // State transition logic
    always @(*) begin
        next_state = A;
        if(reset) begin
            next_state = A;
        end else begin
            case (state)
                A: begin
                    if(in)
                        next_state = B;
                    else
                        next_state = A;
                end
                B: begin
                    if(in)
                        next_state = B;
                    else
                        next_state = C;
                end
                C: begin
                    if(in)
                        next_state = D;
                    else
                        next_state = A;
                end
                D: begin
                    if(in)
                        next_state = B;
                    else
                        next_state = C;
                end
                default: begin
                    next_state = A;
                end
            endcase
        end
    end
    
    // State flip-flops with synchronous reset
    always @(posedge clk) begin
        if(reset)
            state = A;
        else
            state = next_state;
    end
    
    // Output logic
    always @(*) begin
        if(state == D)
            out = 1;
        else 
            out = 0;
    end
endmodule