[MIT6.828] 2: Memory Management

可参考的文章

name	addr.
Lab 2: Memory Management	https://pdos.csail.mit.edu/6.828/2018/labs/lab2/
参考资料	https://pdos.csail.mit.edu/6.828/2018/reference.html
Report for lab2, Houmin Wei	https://github.com/SimpCosm/6.828/tree/master/lab2
6.828 操作系统 lab2 实验报告	https://www.jianshu.com/p/3be92c8228b6
x86_translation_and_registers	https://pdos.csail.mit.edu/6.828/2016/lec/x86_translation_and_registers.pdf
分页原理	https://stackoverflow.com/questions/29945171/difference-between-page-table-and-page-directory
Intel® 64 and IA-32 Architectures Developer’s Manual: Vol. 3A	https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.html

一、如下主要来自stack overflow

In the x86 architecture, page directories and page tables together provide the mapping between virtual addresses (memory addresses used by applications) and physical addresses (actual locations in the physical memory hardware).

A page is simply a contiguous chunk of memory. x86 (32-bit) supports 3 sizes of pages: 4MB, 2MB, and 4KB, with the latter being the most commonly used in mainstream operating systems. A page table is an array of 1024 * 32-bit entries (conveniently fitting into a single 4KB page). Each entry points to the physical address of a page. Because a single page table is not able to represent the entire address space on its own (1024 entries * 4KB = only 22-bits of address space), we require a second level page table: a page directory. A page directory also consists of 1024 * 32-bit entries (again fitting into a single page), each pointing to a page table. We can see that now 1024 * 1024 * 4KB = 32-bits and with this 3-level structure we are able to map the entire 4GB virtual address space.

// A linear address 'la' has a three-part structure as follows:
//
// +--------10------+-------10-------+---------12----------+
// | Page Directory |   Page Table   | Offset within Page  |
// |      Index     |      Index     |                     |
// +----------------+----------------+---------------------+
//  \--- PDX(la) --/ \--- PTX(la) --/ \---- PGOFF(la) ----/
//  \---------- PGNUM(la) ----------/
//
// The PDX, PTX, PGOFF, and PGNUM macros decompose linear addresses as shown.
// To construct a linear address la from PDX(la), PTX(la), and PGOFF(la),
// use PGADDR(PDX(la), PTX(la), PGOFF(la)).

When the CPU is asked to access a virtual address, it uses the 10 highest order bits (31:22) to index into the page directory table (the base address of which is stored in a special register). The next 10 highest order bits (21:12) are used to index into the page table pointed to by the page directory entry. The lowest 12 order bits (11:0) are finally used to index a byte in the page pointed to by the page table entry.

In other systems there may be more or fewer levels of page table required, depending on the size of the virtual address space and the page sizes supported. For example, x86 with 4MB pages only needs a single page directory. In 64-bit mode with 4KB pages, a 4-level system is used: a page mapping level 4 table contains entries that point to one of many page directories.

The Intel Architectures Developer’s Manual has much more information about the topic, particularly in chapters 3 and 4.

二、如下摘自《Intel® 64 and IA-32 Architectures Developer’s Manual: Vol. 3A》

3.1 MEMORY MANAGEMENT OVERVIEW

The memory management facilities of the IA-32 architecture are divided into two parts: segmentation and paging.
Segmentation provides a mechanism of isolating individual code, data, and stack modules so that multiple
programs (or tasks) can run on the same processor without interfering with one another. Paging provides a mech-
anism for implementing a conventional demand-paged, virtual-memory system where sections of a program’s
execution environment are mapped into physical memory as needed. Paging can also be used to provide isolation
between multiple tasks. When operating in protected mode, some form of segmentation must be used. There is
no mode bit to disable segmentation. The use of paging, however, is optional.
These two mechanisms (segmentation and paging) can be configured to support simple single-program (or single-
task) systems, multitasking systems, or multiple-processor systems that used shared memory.
As shown in Figure 3-1, segmentation provides a mechanism for dividing the processor’s addressable memory
space (called the linear address space) into smaller protected address spaces called segments. Segments can
be used to hold the code, data, and stack for a program or to hold system data structures (such as a TSS or LDT).
If more than one program (or task) is running on a processor, each program can be assigned its own set of
segments. The processor then enforces the boundaries between these segments and insures that one program
does not interfere with the execution of another program by writing into the other program’s segments. The
segmentation mechanism also allows typing of segments so that the operations that may be performed on a partic-
ular type of segment can be restricted.
All the segments in a system are contained in the processor’s linear address space. To locate a byte in a particular
segment, a logical address (also called a far pointer) must be provided. A logical address consists of a segment
selector and an offset. The segment selector is a unique identifier for a segment. Among other things it provides an
offset into a descriptor table (such as the global descriptor table, GDT) to a data structure called a segment
descriptor. Each segment has a segment descriptor, which specifies the size of the segment, the access rights and
privilege level for the segment, the segment type, and the location of the first byte of the segment in the linear
address space (called the base address of the segment). The offset part of the logical address is added to the base
address for the segment to locate a byte within the segment. The base address plus the offset thus forms a linear
address in the processor’s linear address space.

3.4 LOGICAL AND LINEAR ADDRESSES

At the system-architecture level in protected mode, the processor uses two stages of address translation to arrive
at a physical address: logical-address translation and linear address space paging.
Even with the minimum use of segments, every byte in the processor’s address space is accessed with a logical
address. A logical address consists of a 16-bit segment selector and a 32-bit offset (see Figure 3-5). The segment
selector identifies the segment the byte is located in and the offset specifies the location of the byte in the segment
relative to the base address of the segment.
The processor translates every logical address into a linear address. A linear address is a 32-bit address in the
processor’s linear address space. Like the physical address space, the linear address space is a flat (unsegmented),
2 32 -byte address space, with addresses ranging from 0 to FFFFFFFFH. The linear address space contains all the
segments and system tables defined for a system.
To translate a logical address into a linear address, the processor does the following:

1. Uses the offset in the segment selector to locate the segment descriptor for the segment in the GDT or LDT and
   reads it into the processor. (This step is needed only when a new segment selector is loaded into a segment
   register.)
2. Examines the segment descriptor to check the access rights and range of the segment to insure that the
   segment is accessible and that the offset is within the limits of the segment.
3. Adds the base address of the segment from the segment descriptor to the offset to form a linear address.
   

3.4.3 Segment Registers

To reduce address translation time and coding complexity, the processor provides registers for holding up to 6
segment selectors (see Figure 3-7). Each of these segment registers support a specific kind of memory reference
(code, stack, or data). For virtually any kind of program execution to take place, at least the code-segment (CS),
data-segment (DS), and stack-segment (SS) registers must be loaded with valid segment selectors. The processor
also provides three additional data-segment registers (ES, FS, and GS), which can be used to make additional data
segments available to the currently executing program (or task).
For a program to access a segment, the segment selector for the segment must have been loaded in one of the
segment registers. So, although a system can define thousands of segments, only 6 can be available for immediate
use. Other segments can be made available by loading their segment selectors into these registers during program
execution.

内存 - 32位的地址空间、4KB的页面和一个4字节PTE是如何推导出4MB的页表？

32的逻辑地址，分成两部分。前部分是代表虚拟的页号，后部分代表的是虚拟页偏移量，如果页面是4KB的话，那么这个后部分虚拟页偏移量占了12位，那么前面就是32-12=20位。这20位就是页表中所有的页表项的和。就是2的20次方，也就是1M个页表项，如果每个页表项占4B的话。那么这个页表就占了4MB的空间。一般都会有两级甚至更多的。用来减少页表占的空间。。。。。

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https://pdos.csail.mit.edu/6.828/2018/labs/lab2/
https://pdos.csail.mit.edu/6.828/2018/reference.html
https://github.com/SimpCosm/6.828/tree/master/lab2
https://www.jianshu.com/p/3be92c8228b6
https://pdos.csail.mit.edu/6.828/2016/lec/x86_translation_and_registers.pdf
https://stackoverflow.com/questions/29945171/difference-between-page-table-and-page-directory