I2C device operation flow

器件通信只使用SCL/SDA。

bus特征，我理解可以认为是device的状态：Bus not Busy，Start Data Transfe，Stop Data Transfer，Data Valid，Acknowledge。

所有的command都在data valid状态传输，每次8bit，

每个command 有效数据8bit后，必须至少等一个clock，等待ack

所有的传输 都以 Start Data Transfe开始，以Stop Data Transfer 结束。中间可以任意多个command。

wirte的操作，结束时ack stop。 ack由device给出，master loop check。

read的操作，结束时noack stop。 ack/noack由master 给出。

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is not busy.

• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1).

4.1 Bus not Busy (A)

Both data and clock lines remain high.

4.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.

4.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line, while the clock (SCL) is high, determines a Stop condition. All operations must end with a Stop condition.

4.4 Data Valid (D)

The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device.

4.5 Acknowledge Each receiving device, when addressed, is obliged to generate an Acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse, which is associated with this Acknowledge bit.

 

参考24AA128器件spec：

http://ww1.microchip.com/downloads/en/devicedoc/21191m.pdf