web bench源码学习3

前面看了下主程序,后面就是一个项目工程中必要的文件了,包括changelog等

changelog

webbench (1.5) unstable; urgency=low

  * allow building with both Gnu and BSD make

 -- Radim Kolar <hsn@home>  Fri, Jun 25 12:00:20 CEST 2004

webbench (1.4) unstable; urgency=low

  * check if url is not too long
  * report correct program version number
  * use yield() when waiting for test start
  * corrected error codes
  * check availability of test server first
  * do not abort test if first request failed
  * report when some childrens are dead.
  * use alarm, not time() for lower syscal use by bench
  * use mode 644 for installed doc
  * makefile cleaned for better freebsd ports integration

 -- Radim Kolar <hsn@home>  Thu, 15 Jan 2004 11:15:52 +0100

webbench (1.3) unstable; urgency=low

  * Build fixes for freeBSD
  * Default benchmark time 60 -> 30
  * generate tar with subdirectory
  * added to freeBSD ports collection

 -- Radim Kolar <hsn@home>  Mon, 12 Jan 2004 17:00:24 +0100

webbench (1.2) unstable; urgency=low

  * Only debian-related bugfixes
  * Updated Debian/rules
  * Adapted to fit new directory system
  * moved from debstd to dh_*

 -- Radim Kolar <hsn@home>  Fri, 18 Jan 2002 12:33:04 +0100

webbench (1.1) unstable; urgency=medium
 
  * Program debianized
  * added support for multiple methods (GET, HEAD, OPTIONS, TRACE)
  * added support for multiple HTTP versions (0.9 -- 1.1)
  * added long options
  * added multiple clients
  * wait for start of second before test
  * test time can be specified
  * better error checking when reading reply from server
  * FIX: tests was one second longer than expected

 -- Radim Kolar <hsn@home>  Thu, 16 Sep 1999 18:48:00 +0200

Local variables:
mode: debian-changelog
End:

版权文件copyright

Webbench was written by Radim Kolar 1997-2004 (hsn@netmag.cz).

UNIX sockets code (socket.c) taken from popclient 1.5 4/1/94 
public domain code, created by Virginia Tech Computing Center.

Copyright: GPL (see /usr/share/common-licenses/GPL)


后续将添加一些测试情况

这些代码可用于以后的库中

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异步FIFO是一种常见的数字电路设计,用来实现数据在不同时钟域之间的传输。Verilog是一种硬件描述语言,用于设计和模拟数字逻辑电路。下面是一个异步FIFO的Verilog源码和相应的测试台代码的示例: Verilog异步FIFO源码: ```verilog module AsyncFIFO ( input wire clk_wr, input wire reset, input wire enable, input wire data_in, output wire full, output wire empty, output reg data_out ); parameter WIDTH = 8; // 数据位宽 parameter DEPTH = 16; // FIFO深度 reg [WIDTH-1:0] memory[0:DEPTH-1]; reg [WIDTH-1:0] read_pointer, write_pointer; always @(posedge clk_wr or posedge reset) begin if (reset) begin read_pointer <= 0; write_pointer <= 0; data_out <= 0; end else if (enable) begin if (~full) begin memory[write_pointer] <= data_in; write_pointer <= write_pointer + 1; end if (~empty) begin data_out <= memory[read_pointer]; read_pointer <= read_pointer + 1; end end end assign full = (write_pointer - read_pointer) == DEPTH; assign empty = (write_pointer == read_pointer); endmodule ``` Verilog异步FIFO测试台代码: ```verilog module AsyncFIFOTest; reg clk_wr; reg reset; reg enable; reg data_in; wire full; wire empty; wire data_out; AsyncFIFO dut ( .clk_wr(clk_wr), .reset(reset), .enable(enable), .data_in(data_in), .full(full), .empty(empty), .data_out(data_out) ); initial begin clk_wr = 0; reset = 1; enable = 0; data_in = 0; #2 reset = 0; // 写入测试数据 #2 enable = 1; #2 data_in = 1; #2; #2 data_in = 2; #2; #2 data_in = 3; #2 enable = 0; // 读取测试数据 #2 enable = 1; #2 enable = 0; // 检查输出数据 $display("data_out: %d", data_out); #2; $display("empty: %b", empty); $finish; end always begin #1 clk_wr = ~clk_wr; end endmodule ``` 以上是一个简单的8位宽、16深度的异步FIFO模块和相应的测试台代码。测试台首先初始化FIFO,然后写入数据1、2、3,最后读取数据并检查输出数据和空状态。 这是一个只包含基本功能的示例,实际应用中可能还需要添加写入满和读取空的异常处理等功能。同时,测试台代码也可以根据具体需求进行修改和扩展以进行更全面的测试。
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