STM32 FDCAN REG 汇总

FDCAN REG

FDCAN_CREL

FDCAN core release register

Bits 31:28 REL[3:0]: 3
Bits 27:24 STEP[3:0]: 2
Bits 23:20 SUBSTEP[3:0]: 1
Bits 19:16 YEAR[3:0]: 4
Bits 15:8 MON[7:0]: 12
Bits 7:0 DAY[7:0]: 18

FDCAN_ENDN

FDCAN endian register

ETV[31:0]: Endianness test value
The endianness test value is 0x8765 4321

FDCAN_DBTP

FDCAN data bit timing and prescaler register

Bits 31:24 Reserved, must be kept at reset value.
Bit 23 TDC: Transceiver delay compensation
	0: Transceiver delay compensation disabled
	1: Transceiver delay compensation enabled
Bits 22:21 Reserved, must be kept at reset value.
Bits 20:16 DBRP[4:0]: Data bit rate prescaler
	The value by which the oscillator frequency is divided to generate the bit time quanta. 
	The bit time is built up from a multiple of this quanta. 
	Valid values for the Baud Rate Prescaler are 0 to 31.
	 The hardware interpreters this value as the value programmed plus 1.
Bits 15:13 Reserved, must be kept at reset value.
Bits 12:8 DTSEG1[4:0]: Data time segment before sample point 
	Valid values are 0 to 31. 
	The value used by the hardware is the one programmed, incremented by 1, i.e. tBS1 = (DTSEG1 + 1) x tq.
Bits 7:4 DTSEG2[3:0]: Data time segment after sample point 
	Valid values are 0 to 15. The value used by the hardware is the one programmed, 
	incremented by 1, i.e. tBS2 = (DTSEG2 + 1) x tq.
Bits 3:0 DSJW[3:0]: Synchronization jump width 
	Must always be smaller than DTSEG2, valid values are 0 to 15. 
	The value used by the hardware is the one programmed, incremented by 1: tSJW = (DSJW + 1) x tq

FDCAN_TEST

FDCAN test register

Bits 31:8 Reserved, must be kept at reset value.
Bit 7 RX: Receive pin
Monitors the actual value of pin FDCANx_RX
	0: The CAN bus is dominant (FDCANx_RX = 0)
	1: The CAN bus is recessive (FDCANx_RX = 1)
Bits 6:5 TX[1:0]: Control of transmit pin
	00: Reset value, FDCANx_TX TX is controlled by the CAN core, 
			updated at the end of the CAN bit time
	01: Sample point can be monitored at pin FDCANx_TX
	10: Dominant (0) level at pin FDCANx_TX
	11: Recessive (1) at pin FDCANx_TX
Bit 4 LBCK: Loop back mode
	0: Reset value, Loop Back mode is disabled
	1: Loop Back mode is enabled (see Power down (Sleep mode))
Bits 3:0 Reserved, must be kept at reset value.

FDCAN_RWD

FDCAN RAM watchdog register

Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 WDV[7:0]: Watchdog value
	Actual message RAM watchdog counter value.
Bits 7:0 WDC[7:0]: Watchdog configuration
	Start value of the message RAM watchdog counter. With the reset value of 00, the counter is disabled.
	These are protected write (P) bits, write access is possible only when the bit [CCE] and bit 0 [INIT] of 
	FDCAN_CCCR register are set to 1

FDCAN_CCCR

FDCAN CC control register

Bits 31:16 Reserved, must be kept at reset value.
Bit 15 NISO: Non ISO operation
	If this bit is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0.
	0: CAN FD frame format according to ISO11898-1
	1: CAN FD frame format according to Bosch CAN FD Specification V1.0
Bit 14 TXP: 
	If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after 
	successfully transmitting a frame.
	0: disabled
	1: enabled
Bit 13 EFBI: Edge filtering during bus integration
	0: Edge filtering disabled
	1: Two consecutive dominant tq required to detect an edge for hard synchronization
Bit 12 PXHD: Protocol exception handling disable
	0: Protocol exception handling enabled
	1: Protocol exception handling disabled
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 BRSE: FDCAN bit rate switching
	0: Bit rate switching for transmissions disabled
	1: Bit rate switching for transmissions enabled
Bit 8 FDOE: FD operation enable
	0: FD operation disabled
	1: FD operation enabled
Bit 7 TEST: Test mode enable
	0: Normal operation, register TEST holds reset values
	1: Test Mode, write access to register TEST enabled
Bit 6 DAR: Disable automatic retransmission
	0: Automatic retransmission of messages not transmitted successfully enabled
	1: Automatic retransmission disabled
Bit 5 MON: Bus monitoring mode
	Bit MON can only be set by software when both CCE and INIT are set to 1. 
	The bit can be reset by the Host at any time.
	0: Bus monitoring mode disabled
	1: Bus monitoring mode enabled
Bit 4 CSR: Clock stop request
	0: No clock stop requested
	1: Clock stop requested. When clock stop is requested, first INIT and then CSA is 
	    set after all pending transfer requests have been completed and the CAN bus reached idle.
Bit 3 CSA: Clock stop acknowledge
	0: No clock stop acknowledged
	1: FDCAN may be set in power down by stopping APB clock and kernel clock
Bit 2 ASM: ASM restricted operation mode
	The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. 
	The application tests different bit rates and leaves the Restricted operation Mode after it has received a 
	valid frame. In the optional Restricted operation Mode the node is able to transmit and receive data and 
	remote frames and it gives acknowledge to valid frames, but it does not send active error frames or 
	overload frames. In case of an error condition or overload condition, it does not send dominant bits, 
	instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication.
	 The error counters are not incremented. Bit ASM can only be set by software when both CCE and 
	 INIT are set to 1. The bit can be reset by the software at any time.
	0: Normal CAN operation
	1: Restricted operation Mode active
Bit 1 CCE: Configuration change enable
	0: The CPU has no write access to the protected configuration registers.
	1: The CPU has write access to the protected configuration registers (while CCCR.INIT = 1).
Bit 0 INIT: Initialization
	0: Normal operation
	1: Initialization started

FDCAN_NBTP

FDCAN nominal bit timing and prescaler register

Bits 31:25 NSJW[6:0]: Nominal (re)synchronization jump width
	Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that 
	the used value is the one programmed incremented by one.These are protected write (P) bits, 
	write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
Bits 24:16 NBRP[8:0]: Bit rate prescaler
	Value by which the oscillator frequency is divided for generating the bit time quanta. The bit time 
	is built up from a multiple of this quanta. Valid values are 0 to 511. The actual interpretation by the 
	hardware of this value is such that one more than the value programmed here is used.
	These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and 
	bit 0 [INIT] of CCCR register are set to 1.
Bits 15:8 NTSEG1[7:0]: Nominal time segment before sample point
	Valid values are 0 to 255. The actual interpretation by the hardware of this value is such that one 
	more than the programmed value is used.These are protected write (P) bits, write access is 
	possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
Bit 7 Reserved, must be kept at reset value.
Bits 6:0 NTSEG2[6:0]: Nominal time segment after sample point
	Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one 
	more than the programmed value is used.

FDCAN_TSCC

FDCAN timestamp counter configuration register

Bits 31:20 Reserved, must be kept at reset value.
Bits 19:16 TCP[3:0]: Timestamp counter prescaler
	Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1 … 16].
	The actual interpretation by the hardware of this value is such that one more than the value 
	programmed here is used.In CAN FD mode the internal timestamp counter TCP does not 
	provide a constant tim