VHDL编程练习——8位双向循环移位寄存器设计及仿真

H2.vhd:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H2 IS
	PORT(CLK,LOAD,M,RESET: IN STD_LOGIC;
							DATA: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
								Q: OUT STD_lOGIC_VECTOR(7 DOWNTO 0));
END ENTITY H2;
ARCHITECTURE HBV OF H2 IS
BEGIN
PROCESS(CLK,RESET,M,LOAD)
VARIABLE Q1 : STD_lOGIC_VECTOR(7 DOWNTO 0);
BEGIN
	IF RESET = '0' THEN  --RESET低电平有效
		Q1 := (OTHERS=>'0');
	ELSIF CLK'EVENT AND CLK='1' THEN
		IF LOAD = '1' THEN
			Q1 := DATA;
		ELSE 
			IF M ='1' THEN
				Q1 := TO_STDLOGICVECTOR(TO_BITVECTOR(Q1) ROL(1));
			ELSIF M ='0' THEN
				Q1 := TO_STDLOGICVECTOR(TO_BITVECTOR(Q1) ROR(1));
			END IF;
		END IF;
	END IF;
	Q<=Q1;
END PROCESS;
END ARCHITECTURE HBV;

激励程序：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TEST IS
END ENTITY;
ARCHITECTURE TEST_H2 OF TEST IS
COMPONENT H2
	PORT(CLK,LOAD,M,RESET: IN STD_LOGIC;
							DATA: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
								Q: OUT STD_lOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
SIGNAL DATA:STD_LOGIC_VECTOR(7 DOWNTO 0):="00100111";
SIGNAL CLK,LOAD,M,RESET: STD_LOGIC;
SIGNAL Q:STD_LOGIC_VECTOR(7 DOWNTO 0);
constant CLK_period : time := 20 ns;
BEGIN
	UUT:H2 PORT MAP(CLK=>CLK,LOAD=>LOAD,M=>M,RESET=>RESET,DATA=>DATA,Q=>Q);
PROCESS --进程1
BEGIN
CLK<='0'; WAIT FOR CLK_period/2;
CLK<='1'; WAIT FOR CLK_period/2;
END PROCESS;
PROCESS --进程2
BEGIN
RESET<='0';
WAIT FOR 100 NS;
RESET<='1';
WAIT;
END PROCESS;
PROCESS --进程3
BEGIN
M<='0'; WAIT FOR 500 NS;
M<='1'; WAIT FOR 500 NS;
END PROCESS;
LOAD<='0','1' AFTER 990 NS,'0' AFTER 1100 NS;
END ARCHITECTURE TEST_H2;

仿真结果：