User 模式 SVC
模式 IRQ
模式 FIQ 模式 APCS
R0 ------- R0 ------- R0 -------
R0 a1
R1 ------- R1 ------- R1 -------
R1 a2
R2 ------- R2 ------- R2 -------
R2 a3
R3 ------- R3 ------- R3 -------
R3 a4
R4 ------- R4 ------- R4 -------
R4 v1
R5 ------- R5 ------- R5 -------
R5 v2
R6 ------- R6 ------- R6 -------
R6 v3
R7 ------- R7 ------- R7 -------
R7 v4
R8 ------- R8 -------
R8 R8_fiq v5
R9 ------- R9 -------
R9 R9_fiq v6
R10 ------ R10 ------
R10 R10_fiq sl
R11 ------ R11 ------
R11 R11_fiq fp
R12 ------ R12 ------
R12 R12_fiq ip
R13 R13_svc R13_irq R13_fiq sp
R14 R14_svc R14_irq R14_fiq lr
------------- R15 / PC
------------- pc
"ARM DeveloperSuite Assembler Guide"
3.3.1 Predeclared register names
The following register names are predeclared:
• r0-r15 and R0-R15
• a1-a4 (argument, result, or scratch registers, synonyms for r0 to
r3)
• v1-v8 (variable registers, r4 to r11)
• sb and SB (static base, r9)
• sl and SL (stack limit, r10)
• fp and FP (frame pointer, r11)
• ip and IP (intra-procedure-call scratch register, r12)
• sp and SP (stack pointer, r13)
• lr and LR (link register, r14)
• pc and PC (program counter, r15).
3.3.2 Predeclared program status register names
The following program status register names are predeclared:
• cpsr and CPSR (current program status register)
• spsr and SPSR (saved program status register).
3.3.3 Predeclared floating-point register names
The following floating-point register names are predeclared:
• f0-f7 and F0-F7 (FPA registers)
• s0-s31 and S0-S31 (VFP single-precision registers)
• d0-d15 and D0-D15 (VFP double-precision registers).
3.3.4 Predeclared coprocessor names
The following coprocessor names and coprocessor register names are
predeclared:
• p0-p15 (coprocessors 0-15)
• c0-c15 (coprocessor registers 0-15).