ARM architecture

ARM architecture

ARM architectures
ARM architecture logo.gif
The ARM logo
DesignerARM Holdings
Bits32-bit or 64-bit
BranchingCondition code
64/32-bit architecture
EncodingAArch64/A64 and AArch32/A32 use 32-bit instructions, T32 (Thumb2) uses mixed 16- and 32-bit instructions. ARMv7 user-space compatibility[1]
EndiannessBi (Little as default)
ExtensionsAll mandatory: Thumb-2NEON,Jazelle, VFPv4-D16, VFPv4
General purpose31x 64-bit integer registers[1] plus PC and SP, ELR, SPSR for exception levels
Floating point32× 128-bit registers,[1]scalar 32- and 64-bit FP,SIMD 64- and 128-bit FP and integer
32-bit architectures (Cortex)
VersionARMv8-R, ARMv7-A, ARMv7-R, ARMv7E-M, ARMv7-M, ARMv6-M
Encoding32-bit except Thumb2 extensions use mixed 16- and 32-bit instructions.
EndiannessBi (Little as default)
ExtensionsThumb-2 (mandatory since ARMv7), NEONJazelle, FPv4-SP
General purpose16x 32-bit integer registers including PC and SP
Floating pointUp to 32× 64-bit registers,[2] SIMD/floating-point (optional)
32-bit architectures (legacy)
VersionARMv6, ARMv5, ARMv4T, ARMv3, ARMv2
Encoding32-bit except Thumb extension uses mixed 16- and 32-bit instructions.
EndiannessBi (Little as default) in ARMv3 and above
General purpose16x 32-bit integer registers including PC (26-bit addressing in older) and SP

ARM is a family of instruction set architectures for computer processors based on a reduced instruction set computing(RISC) architecture developed by British company ARM Holdings.

A RISC-based computer design approach means ARM processors require significantly fewer transistors than typical processors in average computers. This approach reduces costs, heat and power use. These are desirable traits for light, portable, battery-powered devices—including smartphoneslaptopstablet and notepad computers, and other embedded systems. A simpler design facilitates more efficient multi-core CPUs and higher core counts at lower cost, providing higher processing power and improved energy efficiency for servers and supercomputers.[3][4][5]

ARM Holdings develops the instruction set and architecture for ARM-based products, but does not manufacture products. The company periodically releases updates to its cores. Current cores from ARM Holdings support a 32-bit address space and 32-bit arithmetic; the recently introduced ARMv8-A architecture adds support for a 64-bit address space and 64-bit arithmetic. Instructions for ARM Holdings' cores have 32-bit-wide fixed-length instructions, but later versions of the architecture also support a variable-length instruction set that provides both 32-bit and 16-bit-wide instructions for improved code density. Some cores can also provide hardware execution of Java bytecodes.

ARM Holdings licenses the chip designs and the ARM instruction set architectures to third-parties, who design their own products that implement one of those architectures—including systems-on-chips (SoC) that incorporate memory, interfaces, radios, etc. Currently, the widely used Cortex cores, older "classic" cores, and specialized SecurCore cores variants are available for each of these to include or exclude optional capabilities. Companies that produce ARM products include AppleNvidiaQualcommRockchipSamsung Electronics, and Texas Instruments. Apple first implemented the ARMv8-A architecture in the Apple A7 chip in the iPhone 5S.

In 2005, about 98% of all mobile phones sold used at least one ARM processor.[6] The low power consumption of ARM processors has made them very popular: 37 billion ARM processors have been produced as of 2013, up from 10 billion in 2008.[7] The ARM architecture (32-bit) is the most widely used architecture in mobile devices, and most popular 32-bit one in embedded systems.[8]

According to ARM Holdings, in 2010 alone, producers of chips based on ARM architectures reported shipments of 6.1 billion ARM-based processors, representing 95% of smartphones, 35% of digital televisions and set-top boxes and 10% of mobile computers. It is the most widely used 32-bit instruction set architecture in terms of quantity produced.[9][10]




Microprocessor-based system on a chip
The ARM1 second processor for the BBC Micro

The British computer manufacturer Acorn Computers first developed ARM in the 1980s to use in its personal computers. Its first ARM-based products were coprocessor modules for the BBC Micro series of computers. After the successful BBC Micro computer, Acorn Computers considered how to move on from the relatively simple MOS Technology 6502 processor to address business markets like the one that was soon dominated by the IBM PC, launched in 1981. The Acorn Business Computer (ABC) plan required that a number of second processors be made to work with the BBC Micro platform, but processors such as the Motorola 68000 and National Semiconductor 32016 were considered unsuitable, and the 6502 was not powerful enough for a graphics based user interface.[11]

After testing all available processors and finding them lacking, Acorn decided it needed a new architecture. Inspired by white papers on the Berkeley RISC project, Acorn considered designing its own processor.[12] A visit to the Western Design Center in Phoenix, where the 6502 was being updated by what was effectively a single-person company, showed Acorn engineers Steve Furber and Sophie Wilson they did not need massive resources and state-of-the-art research and development facilities.[13]

Wilson developed the instruction set, writing a simulation of the processor in BBC Basic that ran on a BBC Micro with a second 6502 processor. This convinced Acorn engineers they were on the right track. Wilson approached Acorn's CEO, Hermann Hauser, and requested more resources. Once he had approval, he assembled a small team to implement Wilson's model in hardware.

Acorn RISC Machine: ARM2[edit]

The official Acorn RISC Machine project started in October 1983. They chose VLSI Technology as the silicon partner, as they were a source of ROMs and custom chips for Acorn. Wilson and Furber led the design. They implemented it with a similar efficiency ethos as the 6502.[14] A key design goal was achieving low-latency input/output (interrupt) handling like the 6502. The 6502's memory access architecture had let developers produce fast machines without costly direct memory access hardware.

VLSI produced the first ARM silicon on 26 April 1985. It worked the first time, and was known as ARM1 by April 1985.[3] The first production systems named ARM2 were available the following year.

The first practical ARM application was as a second processor for the BBC Micro, where it helped developed simulation software to finish development of the support chips (VIDC, IOC, MEMC), and sped up the CAD software used in ARM2 development. Wilson subsequently rewrote BBC Basic in ARM assembly language. The in-depth knowledge gained from designing the instruction set enabled the code to be very dense, making ARM BBC Basic an extremely good test for any ARM emulator. The original aim of a principally ARM-based computer was achieved in 1987 with the release of the Acorn Archimedes.[15] In 1992, Acorn once more won the Queen's Award for Technology for the ARM.

The ARM2 featured a 32-bit data bus26-bit address space and 27 32-bit registers. 8 bits from the program counter register were available for other purposes; the top 6 bits (available because of the 26-bit address space), served as status flags, and the bottom 2 bits (available because the program counter was always word-aligned), were used for setting modes. The address bus was extended to 32 bits in the ARM6, but program code still had to lie within the first 64 MB of memory in 26-bit compatibility mode, due to the reserved bits for the status flags.[16] The ARM2 had a transistor count of just 30,000, compared to Motorola's six-year-older 68000 model with 68,000.[17] Much of this simplicity came from the lack of microcode (which represents about one-quarter to one-third of the 68000) and from (like most CPUs of the day) not including any cache. This simplicity enabled low power consumption, yet better performance than the Intel 80286. A successor, ARM3, was produced with a 4 KB cache, which further improved performance.[18]

Apple, DEC, Intel, Marvell: ARM6, StrongARM, XScale[edit]

In the late 1980s Apple Computer and VLSI Technology started working with Acorn on newer versions of the ARM core. In 1990, Acorn spun off the design team into a new company named Acorn RISC Machines Ltd., which became ARM Ltd when its parent company, ARM Holdings plc, floated on the London Stock Exchange and NASDAQ in 1998.[19]

The new Apple-ARM work would eventually evolve into the ARM6, first released in early 1992. Apple used the ARM6-based ARM610 as the basis for their Apple Newton PDA. In 1994, Acorn used the ARM610 as the main central processing unit (CPU) in their RiscPC computers. DEC licensed the ARM6 architecture and produced the StrongARM. At 233 MHz, this CPU drew only one watt (newer versions draw far less). This work was later passed to Intel as a part of a lawsuit settlement, and Intel took the opportunity to supplement their i960 line with the StrongARM. Intel later developed its own high performance implementation named XScale, which it has since sold to Marvell. Transistor count of the ARM core remained essentially the same size throughout these changes; ARM2 had 30,000 transistors, while ARM6 grew only to 35,000.[citation needed]


Die of a STM32F103VGT6  ARM Cortex-M3 microcontroller with 1  megabyte  flash memory by  STMicroelectronics.

Core license[edit]

ARM Holdings' primary business is selling IP cores, which licensees use to create microcontrollers (MCUs) and CPUs based on those cores. The original design manufacturer combines the ARM core with other parts to produce a complete CPU, typically one that can be built in existing semiconductor fabs at low cost and still deliver substantial performance. The most successful implementation has been the ARM7TDMI with hundreds of millions sold. Atmel has been a precursor design center in the ARM7TDMI-based embedded system.

The ARM architectures used in smartphones, PDAs and other mobile devices range from ARMv5, used in low-end devices, through ARMv6, to ARMv7 in current high-end devices. ARMv7 includes a hardware floating-point unit (FPU), with improved speed compared to software-based floating-point.

In 2009, some manufacturers introduced netbooks based on ARM architecture CPUs, in direct competition with netbooks based on Intel Atom.[20] According to analyst firm IHS iSuppli, by 2015, ARM ICs may be in 23% of all laptops.[21]

ARM Holdings offers a variety of licensing terms, varying in cost and deliverables. ARM Holdings provides to all licensees an integratable hardware description of the ARM core as well as complete software development toolset (compilerdebugger,software development kit) and the right to sell manufactured silicon containing the ARM CPU.

SoC packages integrating ARM's core designs include Nvidia Tegra's first three generations, CSR plc's Quatro family, ST-Ericsson's Nova and NovaThor, Silicon Labs's Precision32 MCU, Texas Instruments's OMAP products, Samsung's Hummingbird and Exynos products, Apple's A4A5, andA5X, and Freescale's i.MX.

Fabless licensees, who wish to integrate an ARM core into their own chip design, are usually only interested in acquiring a ready-to-manufacture verified IP core. For these customers, ARM Holdings delivers a gate netlist description of the chosen ARM core, along with an abstracted simulation model and test programs to aid design integration and verification. More ambitious customers, including integrated device manufacturers (IDM) and foundry operators, choose to acquire the processor IP in synthesizable RTL (Verilog) form. With the synthesizable RTL, the customer has the ability to perform architectural level optimisations and extensions. This allows the designer to achieve exotic design goals not otherwise possible with an unmodified netlist (high clock speed, very low power consumption, instruction set extensions, etc.). While ARM Holdings does not grant the licensee the right to resell the ARM architecture itself, licensees may freely sell manufactured product such as chip devices, evaluation boards, complete systems. Merchant foundries can be a special case; not only are they allowed to sell finished silicon containing ARM cores, they generally hold the right to re-manufacture ARM cores for other customers.

ARM Holdings prices its IP based on perceived value. Lower performing ARM cores typically have lower licence costs than higher performing cores. In implementation terms, a synthesizable core costs more than a hard macro (blackbox) core. Complicating price matters, a merchant foundry that holds an ARM licence, such as Samsung or Fujitsu, can offer fab customers reduced licensing costs. In exchange for acquiring the ARM core through the foundry's in-house design services, the customer can reduce or eliminate payment of ARM's upfront licence fee.

Compared to dedicated semiconductor foundries (such as TSMC and UMC) without in-house design services, Fujitsu/Samsung charge two- to three-times(2~3) more per manufactured wafer.[citation needed] For low to mid volume applications, a design service foundry offers lower overall pricing (through subsidisation of the licence fee). For high volume mass-produced parts, the long term cost reduction achievable through lower wafer pricing reduces the impact of ARM's NRE (Non-Recurring Engineering) costs, making the dedicated foundry a better choice.

ARM 公司本身并不靠自有的设计来制造或出售 CPU,而是将处理器架构授权给有兴趣的厂家。ARM 提供了多样的授权条款,包括售价与散播性等项目。对于授权方来说,ARM 提供了ARM 内核的整合硬件叙述,包含完整的 软件开发工具编译器debuggerSDK),以及针对内含ARM CPU硅芯片的销售权。对于无晶圆厂的授权方来说,其希望能将ARM 内核整合到他们自行研发的芯片设计中,通常就仅针对取得一份生产就绪的知识产权内核(IP Core)认证。对这些客户来说,ARM 会释出所选的ARM 核心的闸极 电路图,连同抽象模拟模型和测试程式,以协助设计整合和验证。需求更多的客户,包括整合元件制造商( IDM)和 晶圆厂家,就选择可合成的 RTL(暂存器转移层级,如 Verilog)形式来取得处理器的知识产权( IP)。借助可整合的RTL,客户就有能力能进行架构上的最佳化与加强。这个方式能让设计者完成额外的设计目标(如高震荡频率、低能量耗损、指令集延伸等)而不会受限于无法更动的电路图。虽然 ARM 并不授予受权方再次出售ARM 架构本身,但受权方可以任意地出售制品(如芯片元件、评估板、完整系统等)。商用晶圆厂是特殊例子,因为他们不仅授予能出售包含ARM 内核的硅晶成品,对其它客户来讲,他们通常也保留重制ARM 内核的权利。
就像大多数IP 出售方,ARM 依照使用价值来决定IP 的售价。在架构上而言,更低效能的ARM 内核比更高效能的内核拥有较低的授权费。以硅芯片实作而言,一颗可整合的内核要比一颗硬件宏(黑箱)内核要来得贵。更复杂的价位问题来讲,持有ARM 授权的商用晶圆厂(例如韩国 三星和日本 富士通)可以提供更低的授权价格给他们的晶圆厂客户。透过晶圆厂自有的设计技术,客户可以更低或是免费的ARM预付授权费来取得ARM 内核。相较于不具备自有设计技术的专门半导体晶圆厂(如 台积电联电),富士通/三星对每片晶圆多收取了两至三倍的费用。对中少量的应用而言,具备设计部门的晶圆厂提供较低的整体价格(透过授权费用的补助)。对于量产而言,由于长期的成本缩减可借由更低的晶圆价格,减少ARM的 NRE成本,使得专门的晶圆厂也成了一个更好的选择。

Architectural licence[edit]

Companies can also obtain an ARM architectural licence for designing their own CPU cores using the ARM instruction sets. These cores must comply fully with the ARM architecture.


Cores designed by ARM HoldingsCores designed by 3rd partiesCortex profileReferences
ARM8StrongARM, FA526  
ARM7EJARM9EARM10EXScale, FA626TE, Feroceon, PJ1/Mohawk  
ARM Cortex-M0ARM Cortex-M0+ARM Cortex-M1 Microcontroller 
ARM Cortex-M3 
ARM Cortex-M4 
ARM Cortex-R4ARM Cortex-R5ARM Cortex-R7 
ARM Cortex-A5ARM Cortex-A7ARM Cortex-A8,
ARM Cortex-A9ARM Cortex-A12ARM Cortex-A15
KraitScorpion, PJ4/Sheeva, Apple A6/A6X (Swift)
ARM Cortex-A53ARM Cortex-A57[22]X-GeneDenverApple A7 (Cyclone)
[23] [24]
No announcements yet 
[25] [26]

A list of vendors who implement ARM cores in their design (application specific standard products (ASSP), microprocessor and microcontrollers) is provided by ARM Holdings.[27]

Example applications of ARM cores[edit]

Tronsmart MK908, a  Rockchip-based quad-core Android "mini PC", with a microSD card next to it for a size comparison.

ARM cores are used in a number of products, particularly PDAs and smartphones. Some computing examples are the Microsoft Surface, Apple's iPad and ASUS Eee Pad Transformer. Others include Apple's iPhone smartphone and iPod portable media player,Canon PowerShot A470 digital camera, Nintendo DS handheld game console and TomTom turn-by-turn navigation system.

In 2005, ARM Holdings took part in the development of Manchester University's computer, SpiNNaker, which used ARM cores to simulate the human brain.[28]

ARM chips are also used in Raspberry PiBeagleBoardBeagleBonePandaBoard and other single-board computers, because they are very small, inexpensive and consume very little power.

32-bit architecture[edit]

The 32-bit ARM architecture, such as ARMv7-A, is the most widely used architecture in mobile devices.[8]

From 1995, the ARM Architecture Reference Manual has been the primary source of documentation on the ARM processor architecture and instruction set, distinguishing interfaces that all ARM processors are required to support (such as instruction semantics) from implementation details that may vary. The architecture has evolved over time, and version 7 of the architecture, ARMv7, that defines the architecture for the first of the Cortex series of cores, defines three architecture "profiles": 

  • A-profile, the "Application" profile: Cortex-A series
  • R-profile, the "Real-time" profile: Cortex-R series
  • M-profile, the "Microcontroller" profile: Cortex-M series

Although the architecture profiles were first defined for ARMv7, ARM subsequently defined the ARMv6-M architecture (used by the Cortex M0/M0+/M1) as a subset of the ARMv7-M profile with fewer instructions.

CPU modes[edit]

Except in the M-profile, the 32-bit ARM architecture specifies several CPU modes, depending on the implemented architecture features. At any moment in time, the CPU can be in only one mode, but it can switch modes due to external events (interrupts) or programmatically.[29]

User mode
The only non-privileged mode.
FIQ mode
A privileged mode that is entered whenever the processor accepts an FIQ interrupt.
IRQ mode
A privileged mode that is entered whenever the processor accepts an IRQ interrupt.
Supervisor (svc) mode
A privileged mode entered whenever the CPU is reset or when an SVC instruction is executed.
Abort mode
A privileged mode that is entered whenever a prefetch abort or data abort exception occurs.
Undefined mode
A privileged mode that is entered whenever an undefined instruction exception occurs.
System mode (ARMv4 and above)
The only privileged mode that is not entered by an exception. It can only be entered by executing an instruction that explicitly writes to the mode bits of the CPSR.
Monitor mode (ARMv6 and ARMv7 Security Extensions, ARMv8 EL3)
A monitor mode is introduced to support TrustZone extension in ARM cores.
Hyp mode (ARMv7 Virtualization Extensions, ARMv8 EL2)
A hypervisor mode that supports virtualization of the non-secure operation of the CPU. [30]

Instruction set[edit]

The original ARM implementation was hardwired without microcode, like the much simpler 8-bit 6502 processor used in prior Acorn microcomputers.

The 32-bit ARM architecture (and the 64-bit architecture for the most part) includes the following RISC features:

  • Load/store architecture.
  • No support for unaligned memory accesses in the original version of the architecture. ARMv6 and later, except some microcontroller versions, support unaligned accesses for half-word and single-word load/store instructions with some limitations, such as no guaranteed atomicity.[31][32]
  • Uniform 16× 32-bit register file (including the Program Counter, Stack Pointer and the Link Register).
  • Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased code density. Later, the Thumb instruction set added 16-bit instructions and increased code density.
  • Mostly single clock-cycle execution.

To compensate for the simpler design, compared with processors like the Intel 80286 and Motorola 68020, some additional design features were used:

  • Conditional execution of most instructions reduces branch overhead and compensates for the lack of a branch predictor.
  • Arithmetic instructions alter condition codes only when desired.
  • 32-bit barrel shifter can be used without performance penalty with most arithmetic instructions and address calculations.
  • Powerful indexed addressing modes.
  • link register supports fast leaf function calls.
  • A simple, but fast, 2-priority-level interrupt subsystem has switched register banks.

Arithmetic instructions[edit]

The ARM supports add, subtract, and multiply instructions. The integer divide instructions are only implemented by ARM cores based on the following ARM architectures:

  • ARMv7-M and ARMv7E-M architectures always include divide instructions.[33]
  • ARMv7-R architecture always includes divide instructions in the Thumb instruction set, but optionally in its 32-bit instruction set.[34]
  • ARMv7-A architecture optionally includes the divide instructions. The instructions might not be implemented, or implemented only in the Thumb instruction set, or implemented in both the Thumb and ARM instructions sets, or implemented if the Virtualization Extensions are included.[34]


Registers R0 through R7 are the same across all CPU modes; they are never banked.

R13 and R14 are banked across all privileged CPU modes except system mode. That is, each mode that can be entered because of an exception has its own R13 and R14. These registers generally contain the stack pointer and the return address from function calls, respectively.

Registers across CPU modes


  • R13 is also referred to as SP, the Stack Pointer.
  • R14 is also referred to as LR, the Link Register.
  • R15 is also referred to as PC, the Program Counter.

CPSR has the following 32 bits.[35]

  • M (bits 0–4) is the processor mode bits.
  • T (bit 5) is the Thumb state bit.
  • F (bit 6) is the FIQ disable bit.
  • I (bit 7) is the IRQ disable bit.
  • A (bit 8) is the imprecise data abort disable bit.
  • E (bit 9) is the data endianness bit.
  • IT (bits 10–15 and 25–26) is the if-then state bits.
  • GE (bits 16–19) is the greater-than-or-equal-to bits.
  • DNM (bits 20–23) is the do not modify bits.
  • J (bit 24) is the Java state bit.
  • Q (bit 27) is the sticky overflow bit.
  • V (bit 28) is the overflow bit.
  • C (bit 29) is the carry/borrow/extend bit.
  • Z (bit 30) is the zero bit.
  • N (bit 31) is the negative/less than bit.

Conditional execution[edit]

Almost every ARM instruction has a conditional execution feature called predication, which is implemented with a 4-bit condition code selector (the predicate). To allow for unconditional execution, one of the four-bit codes causes the instruction to be always executed. Most other CPU architectures only have condition codes on branch instructions.

Though the predicate takes up 4 of the 32 bits in an instruction code, and thus cuts down significantly on the encoding bits available for displacements in memory access instructions, it avoids branch instructions when generating code for small if statements. Apart from eliminating the branch instructions themselves, this preserves the fetch/decode/execute pipeline at the cost of only one cycle per skipped instruction.

The standard example of conditional execution is the subtraction-based Euclidean algorithm:

In the C programming language, the loop is:

    while (i != j)
       if (i > j)
           i -= j;
       else  /* i < j (since i != j in while condition) */
           j -= i;

In ARM assembly, the loop is:

loop:   CMP  Ri, Rj         ; set condition "NE" if (i != j),
                            ;               "GT" if (i > j),
                            ;            or "LT" if (i < j)
        SUBGT  Ri, Ri, Rj   ; if "GT" (Greater Than), i = i-j;
        SUBLT  Rj, Rj, Ri   ; if "LT" (Less Than), j = j-i;
        BNE  loop           ; if "NE" (Not Equal), then loop

which avoids the branches around the then and else clauses. If Ri and Rj are equal then neither of the SUB instructions will be executed, eliminating the need for a conditional branch to implement the while check at the top of the loop, for example had SUBLE (less than or equal) been used.

One of the ways that Thumb code provides a more dense encoding is to remove the four bit selector from non-branch instructions.

Other features[edit]

Another feature of the instruction set is the ability to fold shifts and rotates into the "data processing" (arithmetic, logical, and register-register move) instructions, so that, for example, the C statement

a += (j << 2);

could be rendered as a single-word, single-cycle instruction:[36]

ADD  Ra, Ra, Rj, LSL #2

This results in the typical ARM program being denser than expected with fewer memory accesses; thus the pipeline is used more efficiently.

The ARM processor also has features rarely seen in other RISC architectures, such as PC-relative addressing (indeed, on the 32-bit[1] ARM the PC is one of its 16 registers) and pre- and post-increment addressing modes.

The ARM instruction set has increased over time. Some early ARM processors (before ARM7TDMI), for example, have no instruction to store a two-byte quantity.

Pipelines and other implementation issues[edit]

The ARM7 and earlier implementations have a three-stage pipeline; the stages being fetch, decode and execute. Higher-performance designs, such as the ARM9, have deeper pipelines: Cortex-A8 has thirteen stages. Additional implementation changes for higher performance include a faster adder and more extensive branch prediction logic. The difference between the ARM7DI and ARM7DMI cores, for example, was an improved multiplier; hence the added "M".


The ARM architecture provides a non-intrusive way of extending the instruction set using "coprocessors" that can be addressed using MCR, MRC, MRRC, MCRR, and similar instructions. The coprocessor space is divided logically into 16 coprocessors with numbers from 0 to 15, coprocessor 15 (cp15) being reserved for some typical control functions like managing the caches and MMU operation on processors that have one.

In ARM-based machines, peripheral devices are usually attached to the processor by mapping their physical registers into ARM memory space, into the coprocessor space, or by connecting to another device (a bus) that in turn attaches to the processor. Coprocessor accesses have lower latency, so some peripherals—for example an XScale interrupt controller—are accessible in both ways: through memory and through coprocessors.

In other cases, chip designers only integrate hardware using the coprocessor mechanism. For example, an image processing engine might be a small ARM7TDMI core combined with a coprocessor that has specialised operations to support a specific set of HDTV transcoding primitives.


All modern ARM processors include hardware debugging facilities, allowing software debuggers to perform operations such as halting, stepping, and breakpointing of code starting from reset. These facilities are built using JTAG support, though some newer cores optionally support ARM's own two-wire "SWD" protocol. In ARM7TDMI cores, the "D" represented JTAG debug support, and the "I" represented presence of an "EmbeddedICE" debug module. For ARM7 and ARM9 core generations, EmbeddedICE over JTAG was a de facto debug standard, though not architecturally guaranteed.

The ARMv7 architecture defines basic debug facilities at an architectural level. These include breakpoints, watchpoints and instruction execution in a "Debug Mode"; similar facilities were also available with EmbeddedICE. Both "halt mode" and "monitor" mode debugging are supported. The actual transport mechanism used to access the debug facilities is not architecturally specified, but implementations generally include JTAG support.

There is a separate ARM "CoreSight" debug architecture, which is not architecturally required by ARMv7 processors.


The ARM architecture is supported by a set of development tools such as Emprog ThunderBench for ARM. Such tools allow development engineers to program the ARM architecture device using a high level language like C.[37]

DSP enhancement instructions[edit]

To improve the ARM architecture for digital signal processing and multimedia applications, DSP instructions were added to the set.[38] These are signified by an "E" in the name of the ARMv5TE and ARMv5TEJ architectures. E-variants also imply T,D,M and I.

The new instructions are common in digital signal processor architectures. They include variations on signed multiply–accumulate, saturated add and subtract, and count leading zeros.

SIMD extensions for multimedia[edit]

Introduced in ARMv6 architecture.[39]


Jazelle DBX (Direct Bytecode eXecution) is a technique that allows Java Bytecode to be executed directly in the ARM architecture as a third execution state (and instruction set) alongside the existing ARM and Thumb-mode. Support for this state is signified by the "J" in the ARMv5TEJ architecture, and in ARM9EJ-S and ARM7EJ-S core names. Support for this state is required starting in ARMv6 (except for the ARMv7-M profile), though newer cores only include a trivial implementation that provides no hardware acceleration.


To improve compiled code-density, processors since the ARM7TDMI (released in 1994[40]) have featured Thumb instruction set, which have their own state. (The "T" in "TDMI" indicates the Thumb feature.) When in this state, the processor executes the Thumb instruction set, a compact 16-bit encoding for a subset of the ARM instruction set.[41] Most of the Thumb instructions are directly mapped to normal ARM instructions. The space-saving comes from making some of the instruction operands implicit and limiting the number of possibilities compared to the ARM instructions executed in the ARM instruction set state.

In Thumb, the 16-bit opcodes have less functionality. For example, only branches can be conditional, and many opcodes are restricted to accessing only half of all of the CPU's general-purpose registers. The shorter opcodes give improved code density overall, even though some operations require extra instructions. In situations where the memory port or bus width is constrained to less than 32 bits, the shorter Thumb opcodes allow increased performance compared with 32-bit ARM code, as less program code may need to be loaded into the processor over the constrained memory bandwidth.

Embedded hardware, such as the Game Boy Advance, typically have a small amount of RAM accessible with a full 32-bit datapath; the majority is accessed via a 16-bit or narrower secondary datapath. In this situation, it usually makes sense to compile Thumb code and hand-optimise a few of the most CPU-intensive sections using full 32-bit ARM instructions, placing these wider instructions into the 32-bit bus accessible memory.

The first processor with a Thumb instruction decoder was the ARM7TDMI. All ARM9 and later families, including XScale, have included a Thumb instruction decoder.


Thumb-2 technology was introduced in the ARM1156 core, announced in 2003. Thumb-2 extends the limited 16-bit instruction set of Thumb with additional 32-bit instructions to give the instruction set more breadth, thus producing a variable-length instruction set. A stated aim for Thumb-2 was to achieve code density similar to Thumb with performance similar to the ARM instruction set on 32-bit memory. In ARMv7 this goal can be said to have been met.[citation needed]

Thumb-2 extends the Thumb instruction set with bit-field manipulation, table branches and conditional execution. At the same time, the ARM instruction set was extended to maintain equivalent functionality in both instruction sets. A new "Unified Assembly Language" (UAL) supports generation of either Thumb or ARM instructions from the same source code; versions of Thumb seen on ARMv7 processors are essentially as capable as ARM code (including the ability to write interrupt handlers). This requires a bit of care, and use of a new "IT" (if-then) instruction, which permits up to four successive instructions to execute based on a tested condition, or on its inverse. When compiling into ARM code this is ignored, but when compiling into Thumb it generates an actual instruction. For example:

; if (r0 == r1)
CMP r0, r1
ITE EQ        ; ARM: no code ... Thumb: IT instruction
; then r0 = r2;
MOVEQ r0, r2  ; ARM: conditional; Thumb: condition via ITE 'T' (then)
; else r0 = r3;
MOVNE r0, r3  ; ARM: conditional; Thumb: condition via ITE 'E' (else)
; recall that the Thumb MOV instruction has no bits to encode "EQ" or "NE"

All ARMv7 chips support the Thumb instruction set. All chips in the Cortex-A series, Cortex-R series, and ARM11 series support both "ARM instruction set state" and "Thumb instruction set state", while chips in the Cortex-M series support only the Thumb instruction set.[42][43][44]

Thumb Execution Environment (ThumbEE)[edit]

ThumbEE (erroneously called Thumb-2EE in some ARM documentation), marketed as Jazelle RCT (Runtime Compilation Target), was announced in 2005, first appearing in the Cortex-A8 processor. ThumbEE is a fourth Instruction set state, making small changes to the Thumb-2 extended Thumb instruction set. These changes make the instruction set particularly suited to code generated at runtime (e.g. by JIT compilation) in managed Execution Environments. ThumbEE is a target for languages such as JavaC#Perl, and Python, and allows JIT compilers to output smaller compiled code without impacting performance. 

New features provided by ThumbEE include automatic null pointer checks on every load and store instruction, an instruction to perform an array bounds check, and special instructions that call a handler. In addition, because it utilises Thumb-2 technology, ThumbEE provides access to registers r8-r15 (where the Jazelle/DBX Java VM state is held).[45] Handlers are small sections of frequently called code, commonly used to implement high level languages, such as allocating memory for a new object. These changes come from repurposing a handful of opcodes, and knowing the core is in the new ThumbEE Instruction set state.

On 23 November 2011, ARM Holdings deprecated any use of the ThumbEE instruction set,[46] and ARMv8 removes support for ThumbEE.

Floating-point (VFP)[edit]

VFP (Vector Floating Point) technology is an FPU coprocessor extension to the ARM architecture. It provides low-cost single-precision and double-precision floating-point computation fully compliant with the ANSI/IEEE Std 754-1985 Standard for Binary Floating-Point Arithmetic. VFP provides floating-point computation suitable for a wide spectrum of applications such as PDAs, smartphones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecture was intended to support execution of short "vector mode" instructions but these operated on each vector element sequentially and thus did not offer the performance of true single instruction, multiple data (SIMD) vector parallelism. This vector mode was therefore removed shortly after its introduction,[47] to be replaced with the much more powerful NEON Advanced SIMD unit.

Some devices such as the ARM Cortex-A8 have a cut-down VFPLite module instead of a full VFP module, and require roughly ten times more clock cycles per float operation.[48] Other floating-point and/or SIMD coprocessors found in ARM-based processors include FPA, FPE, iwMMXt. They provide some of the same functionality as VFP but are not opcode-compatible with it.

An optional extension to the ARM instruction set in the ARMv5TE, ARMv5TEJ and ARMv6 architectures.
VFPv3 or VFPv3-D32
Implemented on earlier ARMv7 processors (Cortex-A8 and A9) and is backwards compatible with VFPv2, except that it cannot trap floating-point exceptions. VFPv3 has 32x 64-bit FPU registers as standard, adds VCVT instructions to convert between scalar, float and double, adds immediate mode to VMOV such that constants can be loaded into FPU registers.
As above, but it has only 16 64-bit FPU registers.
Uncommon; it supports  IEEE754-2008 half-precision (16-bit) floating point.
VFPv4 or VFPv4-D32
Is implemented on later ARMv7 processors (Cortex-A12 and A15). VFPv4 has 32x 64-bit FPU registers as standard, adds both half-precision extensions and  fused multiply-accumulate instructions to the features of VFPv3.
As above, but it has only 16x 64-bit FPU registers. Implemented on Cortex-A5 and A7 processors.

In Debian Linux and derivatives armhf (ARM hard float) refers to the ARMv7 architecture including the additional VFP3-D16 floating-point hardware extension (and Thumb-2) above. Software packages and cross-compiler tools use the armhf vs. arm/armel suffixes to differentiate.[49]

Advanced SIMD (NEON)[edit]

The Advanced SIMD extension (aka NEON or "MPE" Media Processing Engine) is a combined 64- and 128-bit SIMD instruction set that provides standardized acceleration for media and signal processing applications. NEON is included in all Cortex-A8 devices but is optional in Cortex-A9 devices.[50] NEON can execute MP3 audio decoding on CPUs running at 10 MHz and can run the GSM adaptive multi-rate (AMR) speech codec at no more than 13 MHz. It features a comprehensive instruction set, separate register files and independent execution hardware.[51] NEON supports 8-, 16-, 32- and 64-bit integer and single-precision (32-bit) floating-point data and SIMD operations for handling audio and video processing as well as graphics and gaming processing. In NEON, the SIMD supports up to 16 operations at the same time. The NEON hardware shares the same floating-point registers as used in VFP. Devices such as the ARM Cortex-A8 and Cortex-A9 support 128-bit vectors but will execute with 64 bits at a time,[48] whereas newer Cortex-A15 devices can execute 128 bits at a time.

ProjectNe10 is ARM's first open source project (from its inception). The Ne10 library is a set of common, useful functions written in both NEON and C (for compatibility). The library was created to allow developers to use NEON optimizations without learning NEON but it also serves as a set of highly optimized NEON intrinsic and assembly code examples for common DSP, arithmetic and image processing routines. The code is available on GitHub.  

Security extensions (TrustZone)[edit]

The Security Extensions, marketed as TrustZone Technology, is in ARMv6KZ and later application profile architectures. It provides a low cost alternative to adding an additional dedicated security core to an SoC, by providing two virtual processors backed by hardware based access control. This lets the application core switch between two states, referred to as worlds (to reduce confusion with other names for capability domains), in order to prevent information from leaking from the more trusted world to the less trusted world. This world switch is generally orthogonal to all other capabilities of the processor, thus each world can operate independently of the other while using the same core. Memory and peripherals are then made aware of the operating world of the core and may use this to provide access control to secrets and code on the device.

Typical applications of TrustZone Technology are to run a rich operating system in the less trusted world, and smaller security-specialized code in the more trusted world (named TrustZone Software, a TrustZone optimised version of the Trusted Foundations Software developed by Trusted Logic Mobility), allowing much tighter digital rights management for controlling the use of media on ARM-based devices,[52] and preventing any unapproved use of the device. Trusted Foundations Software was acquired by Gemalto. Giesecke & Devrient developed a rival implementation named Mobicore. In April 2012 ARM Gemalto and Giesecke & Devrient combined their TrustZone portfolios into a joint venture Trustonic.[53][54] Open Virtualization is an open source implementation of the trusted world architecture for TrustZone.[55] 

In practice, since the specific implementation details of TrustZone are proprietary and have not been publicly disclosed for review, it is unclear what level of assurance is provided for a given threat model.[citation needed]

No-execute page protection[edit]

As of ARMv6, the ARM architecture supports no-execute page protection, which is referred to as XN, for eXecute Never.[56]


The ARMv8-R subarchitecture announced after the ARMv8-A shares some features except that it is not 64-bit.

64/32-bit architecture[edit]


Announced in October 2011,[57] ARMv8-A (often called ARMv8 although not all variants are 64-bit such as ARMv8-R) represents a fundamental change to the ARM architecture. It adds a 64-bit architecture, named "AArch64", and a new "A64" instruction set. AArch64 provides user-space compatibility with ARMv7-A ISA, the 32-bit architecture, therein referred to as "AArch32" and the old 32-bit instruction set, now named "A32". The Thumb instruction sets are referred to as "T32" and have no 64-bit counterpart. ARMv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit hypervisor.[1] ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012.[22]

To both AArch32 and AArch64, ARMv8-A makes VFPv3/v4 and advanced SIMD (NEON) standard. It also adds cryptography instructions supporting AES and SHA-1/SHA-256.

AArch64 features[edit]

  • New instruction set, A64
    • Has 31 general-purpose 64-bit registers.
    • Has separate dedicated SP and PC.
    • Instructions are still 32 bits long and mostly the same as A32 (with LDM/STM instructions and most conditional execution dropped).
      • Has paired loads/stores (in place of LDM/STM).
    • Most instructions can take 32-bit or 64-bit arguments.
    • Addresses assumed to be 64-bit.
  • Advanced SIMD (NEON) enhanced
    • Has 32× 128-bit registers (up from 16), also accessible via VFPv4.
    • Supports double-precision floating point.
    • Fully IEEE 754 compliant
    • AES encrypt/decrypt and SHA-1/SHA-2 hashing instructions also use these registers.
  • A new exception system
    • Fewer banked registers and modes.
  • Memory translation from 48-bit virtual addresses based on the existing LPAE, which was designed to be easily extended to 64-bit.

Operating system support[edit]

32-bit operating systems[edit]

Android, a  popular operating system running on the ARM architecture.
Historical operating systems
The first ARM-based personal computer, the Acorn Archimedes, ran an interim operating system called  Arthur, which evolved into  RISC OS, used on later ARM-based systems from Acorn and other vendors. Some Acorn machines also had a  Unix port called  RISC iX.
Embedded operating systems
The ARM architecture is supported by a large number of  embedded and  real-time operating systems, including  LinuxWindows CE, SymbianChibiOS/RTFreeRTOSeCosIntegrityNucleus PLUSMicroC/OS-IIPikeOS, [58]  QNXRTEMSRTXC QuadrosThreadX, VxWorksDRYOSMQXT-KernelOSESCIOPTA and RISC OS.
Mobile device operating systems
The ARM architecture is the primary hardware environment for most mobile device operating systems such as iOS,  AndroidWindows PhoneWindows RTBadaBlackberry OS/ Blackberry 10MeeGoFirefox OSTizenUbuntu TouchSailfish and  Igelle OS.
Desktop operating systems
The ARM architecture is supported by RISC OS and multiple  Unix-like operating systems including  BSD and various  Linux distributions such as  Ubuntu and  Chrome OS.

64-bit operating systems[edit]

Mobile device operating systems
iOS 7 on the 64-bit  Apple A7 SOC has ARMv8-A application support.
Desktop operating systems
Patches to the  Linux kernel adding ARMv8-A support have been posted for review by Catalin Marinas of ARM Ltd. The patches have been included in kernel version 3.7 in late 2012. [59] ARMv8-A is supported by some  Linux distributions.

See also[edit]

  • Unicore, a 32-register architecture based heavily on a 32-bit ARM.

Comparison of current ARM cores

From Wikipedia, the free encyclopedia

This list provides an overview of the properties of ARM architecture microprocessor cores.

 ARM11ARM Cortex-A5ARM Cortex-A7ARM Cortex-A8ARM Cortex-A9Qualcomm ScorpionQualcomm Krait[1]ARM Cortex-A15 MPCore
Pipeline depth8 stages 8 stages13 stages8 stages10 stages11 stages15/17-25 stages
Out-of-order executionNoNoNoNoYesnon-speculative[2]YesYes
FPUVFPv2VFPv4 (optional)VFPv4VFPv3VFPv3 (optional)VFPv3VFPv4[3]VFPv4
Pipelined VFPYes YesNoYesYesYesYes
FPU registers32× 32-bit16 × 64-bit16 × 64-bit32 × 64-bit(16 or 32) × 64-bit  32 × 64-bit


No64-bit wide (optional)64-bit wide64-bit wide64-bit wide (optional)128-bit wide128-bit wide128-bit wide
Execution ports     37 
Process technology90/65/45 nm 40/28 nm65/55/45 nm65/45/40/32/28 nm65/45 nm28 nm32/28 nm
L0 cache      KB + 4 KB direct mapped 
L1 cacheVarying, typically 16 KB + 16 KB4-64 KB / core8-64 KB / core32 KB + 32 KB32 KB + 32 KB32 KB + 32 KB16 KB + 16 KB 4-way set associative32 KB + 32 KB per core
L2 cacheVarying, typically none up to 1 MB(optional)256 or 512 (typical) KB1 MB256 KB (Single-core)/512 KB (Dual-core)1 MB 8-way set associative (Dual-core)/2 MB (Quad-core)up to 4 MB per cluster, up to 8 KMB per chip
Core configurations11, 2, 41, 2, 4, 811, 2, 41, 22, 42, 4, 8 (4×2)
Speed per core (DMIPS/MHz)1.251.571. (Krait) / 3.1 (Krait 200) / 3.4 (Krait 300)[4] / 3.6 (Krait 400)3.5



List of ARM cores

From Wikipedia, the free encyclopedia
This is a sub-article to ARM architecture.

This is a list of ARM architecture-based microprocessor cores by ARM Holdings and 3rd parties, sorted by generation release and name. ARM provides a summary of the numerous vendors who implement ARM cores in their design.[1] Keil also provides a somewhat newer summary of vendors of ARM based processors.[2] ARM further provides a chart[3] displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM core families.

ARM cores[edit]

Designed by ARM[edit]

ARM FamilyARM ArchitectureARM CoreFeatureCache (I / D), MMUTypical MIPS @ MHz
ARM1ARMv1ARM1First implementationNone 
ARM2ARMv2ARM2ARMv2 added the MUL (multiply) instructionNone4 MIPS @ 8 MHz
0.33 DMIPS/MHz
ARMv2aARM250Integrated MEMC (MMU), Graphics and IO processor. ARMv2a added the SWP and SWPB (swap) instructions.None, MEMC1a7 MIPS @ 12 MHz
ARM3ARMv2aARM3First integrated memory cache.KB unified12 MIPS @ 25 MHz
0.50 DMIPS/MHz
ARM6ARMv3ARM60ARMv3 first to support 32-bit memory address space (previously 26-bit)None10 MIPS @ 12 MHz
ARM600As ARM60, cache and coprocessor bus (for FPA10 floating-point unit).4 KB unified28 MIPS @ 33 MHz
ARM610As ARM60, cache, no coprocessor bus.4 KB unified17 MIPS @ 20 MHz
0.65 DMIPS/MHz
ARM7ARMv3ARM700 8 KB unified40 MHz
ARM710As ARM700, no coprocessor bus.8 KB unified40 MHz
ARM710aAs ARM7108 KB unified40 MHz
0.68 DMIPS/MHz
ARM7TDMIARMv4TARM7TDMI(-S)3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bit addressingnone15 MIPS @ 16.8 MHz
63 DMIPS @ 70 MHz
ARM710TAs ARM7TDMI, cache8 KB unified, MMU36 MIPS @ 40 MHz
ARM720TAs ARM7TDMI, cache8 KB unified, MMU with Fast Context Switch Extension60 MIPS @ 59.8 MHz
ARM7EJARMv5TEJARM7EJ-S5-stage pipeline, Thumb, Jazelle DBX, Enhanced DSP instructionsnone 
ARM8ARMv4ARM810[4][5]5-stage pipeline, static branch prediction, double-bandwidth memory8 KB unified, MMU84 MIPS @ 72 MHz
1.16 DMIPS/MHz
ARM9TDMIARMv4TARM9TDMI5-stage pipeline, Thumbnone 
ARM920TAs ARM9TDMI, cache16 KB / 16 KB, MMU with FCSE (Fast Context Switch Extension)[6]200 MIPS @ 180 MHz
ARM922TAs ARM9TDMI, caches8 KB / 8 KB, MMU 
ARM940TAs ARM9TDMI, caches4 KB / 4 KB, MPU 
ARM9EARMv5TEARM946E-SThumb, Enhanced DSP instructions, cachesvariable, tightly coupled memories, MPU 
ARM966E-SThumb, Enhanced DSP instructionsno cache, TCMs 
ARM968E-SAs ARM966E-Sno cache, TCMs 
ARMv5TEJARM926EJ-SThumb, Jazelle DBX, Enhanced DSP instructionsvariable, TCMs, MMU220 MIPS @ 200 MHz
ARMv5TEARM996HSClockless processor, as ARM966E-Sno caches, TCMs, MPU 
ARM10EARMv5TEARM1020E6-stage pipeline, Thumb, Enhanced DSP instructions, (VFP)32 KB / 32 KB, MMU 
ARM1022EAs ARM1020E16 KB / 16 KB, MMU 
ARMv5TEJARM1026EJ-SThumb, Jazelle DBX, Enhanced DSP instructions, (VFP)variable, MMU or MPU 
ARM11ARMv6ARM1136J(F)-S[7]8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), Enhanced DSP instructionsvariable, MMU740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz
ARMv6T2ARM1156T2(F)-S8-stage pipeline, SIMD, Thumb-2, (VFP), Enhanced DSP instructionsvariable, MPU 
ARMv6ZARM1176JZ(F)-SAs ARM1136EJ(F)-Svariable, MMU + TrustZone965 DMIPS @ 772 MHz, up to 2 600 DMIPS with four processors[8]
ARMv6KARM11 MPCoreAs ARM1136EJ(F)-S, 1–4 core SMPvariable, MMU 
SecurCoreARMv6-MSC000  0.9 DMIPS/MHz
ARMv7-MSC300  1.25 DMIPS/MHz
Cortex-MARMv6-MCortex-M0 [9]Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),[10] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryNo cache, No TCM, No MPU0.84 DMIPS/MHz
Cortex-M0+[11]Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),[10] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryNo cache, No TCM, optional MPU with 8 regions0.93 DMIPS/MHz
Cortex-M1[12]Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),[10] hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memoryNo cache, 0-1024 KB I-TCM, 0-1024 KB D-TCM, No MPU136 DMIPS @ 170 MHz,[13] (0.8 DMIPS/MHz FPGA-dependent)[14]
ARMv7-MCortex-M3[15]Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memoryNo cache, No TCM, optional MPU with 8 regions1.25 DMIPS/MHz
ARMv7E-MCortex-M4[16]Microcontroller profile, Thumb / Thumb-2 / DSP / optional FPv4 single-precision FPU, hardware multiply and divide instructions, optional bit-banding memoryNo cache, No TCM, optional MPU with 8 regions1.25 DMIPS/MHz
Cortex-RARMv7-RCortex-R4[17]Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic0-64 KB / 0-64 KB, 0-2 of 0-8 MB TCM, opt MPU with 8/12 regions 
Cortex-R5 (MPCore) [18]Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP) [19]0-64 KB / 0-64 KB, 0-2 of 0-8 MB TCM, opt MPU with 12/16 regions 
Cortex-R7 (MPCore) [20]Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamicregister renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP [19]0-64 KB / 0-64 KB, ? of 0-128 KB TCM, opt MPU with 16 regions 
Cortex-AARMv7-ACortex-A5[21]Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)4-64 KB / 4-64 KB L1, MMU + TrustZone1.57 DMIPS / MHz per core
Cortex-A7 MPCore [22]Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4-D16 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, architecture and feature set are identical to A15, 8-10 stage pipeline, low-power design[23]32 KB / 32 KB L1, 0-4 MB L2, MMU + TrustZone1.9 DMIPS / MHz per core
Cortex-A8[24]Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stagesuperscalar pipeline16-32 KB / 16-32 KB L1, 0-1 MB L2 opt ECC, MMU + TrustZoneup to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)
Cortex-A9 MPCore [25]Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1–4 SMP cores, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)16-64 KB / 16-64 KB L1, 0-8 MB L2 opt parity, MMU + TrustZone2.5 DMIPS/MHz per core, 10,000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G(dual core)
ARM Cortex-A12 [26]Application profile, ARM / Thumb-2 / DSP / VFPv4 FPU / NEON / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)32-64 KB / 32 KB L1, 256 KB-8 MB L23.0 DMIPS / MHz per core
Cortex-A15 MPCore [27]Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Integer divide / Fused MAC / Jazelle RCT / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline[23]32 KB I$ w/parity / 32 KB D$ w/ECC L1, 0-4 MB L2, L2 has ECC, MMU + TrustZoneAt least 3.5 DMIPS/MHz per core (Up to 4.01 DMIPS/MHz depending on implementation).[28]
Cortex-A50ARMv8-ACortex-A53[29]Application profile, AArch32 and AArch64, 1-4 SMP cores, Trustzone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline8-64 KB w/parity / 8-64 KB w/ECC L1 per core, 128 KB-2 MB L2 shared, 40-bit physical addresses2.3 DMIPS/MHz
Cortex-A57[30]Application profile, AArch32 and AArch64, 1-4 SMP cores, Trustzone, NEON advanced SIMD, VFPv4, hardware virtualization, multi-issue, deeply out-of-order pipeline48 KB w/DED parity / 32 KB w/ECC L1 per core, 512 KB-2 MB L2 shared, 44-bit physical addressesAt least 4.1 DMIPS/MHz per core (Up to 4.76 DMIPS/MHz depending on implementation).
ARM FamilyARM ArchitectureARM CoreFeatureCache (I / D), MMUTypical MIPS @ MHz

Designed by third parties[edit]

These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.

FamilyARM ArchitectureCoreFeatureCache (I / D), MMUTypical MIPS @ MHz
StrongARMARMv4SA-1105-stage pipeline16 KB / 16 KB, MMU100-206 MHz
SA-1100derivative of the SA-11016 KB / 8 KB, MMU 
Faraday[31]ARMv4FA5106-stage pipelineup to 32 KB / 32 KB Cache, MPU1.26 DMIPS/MHz
100-200 MHz
FA526up to 32 KB / 32 KB Cache, MMU1.26 MIPS/MHz
166-300 MHz
FA6268-stage pipeline32 KB / 32 KB Cache, MMU1.35 DMIPS/MHz
500 MHz
ARMv5TEFA606TE5-stage pipelineno cache, no MMU1.22 DMIPS/MHz
200 MHz
FA626TE8-stage pipeline32 KB / 32 KB Cache, MMU1.43 MIPS/MHz
800 MHz
FMP626TE8-stage pipeline, SMP1.43 MIPS/MHz
500 MHz
FA726TE13 stage pipeline, dual issue2.4 DMIPS/MHz
1000 MHz
XScaleARMv5TEXScale7-stage pipeline, Thumb, Enhanced DSP instructions32 KB / 32 KB, MMU133–400 MHz
BulverdeWireless MMX, Wireless SpeedStep added32 KB / 32 KB, MMU312–624 MHz
Monahans[32]Wireless MMX2 added32 KB / 32 KB (L1), optional L2 cache up to 512 KB, MMUup to 1.25 GHz
SheevaARMv5Feroceon5-8 stage pipeline, single-issue16 KB / 16 KB, MMU600-2000 MHz
Jolteon5-8 stage pipeline, dual-issue32 KB / 32 KB, MMU
PJ1 (Mohawk)5-8 stage pipeline, single-issue, Wireless MMX232 KB / 32 KB, MMU1.46 DMIPS/MHz
1.06 GHz
ARMv6 / ARMv7-APJ46-9 stage pipeline, dual-issue, Wireless MMX2, SMP32 KB / 32 KB, MMU2.41 DMIPS/MHz
1.6 GHz
SnapdragonARMv7-AScorpion [33]1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON (128-bit wide)256 KB L2 per core2.1 DMIPS / MHz per core
Krait [33]1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON (128-bit wide)4 KB / 4 KB L0, 16 KB / 16 KB L1, 512 KB L2 per core3.3 DMIPS / MHz per core
Apple A6,
Apple A6X
ARMv7-AApple Swift[34]2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEONL1: 32 KB / 32 KB, L2: 1 MB3.5 DMIPS / MHz Per Core
Apple A7ARMv8-AApple Cyclone2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON /TrustZone / AArch64L1: 64 KB / 64 KB, L2: 1 MB 
X-GeneARMv8-AX-Gene64 bit, quad issue, SMPCache, MMU, Virtualization3 GHz
DenverARMv8-AParker64 bit

ARM Cortex-A8

From Wikipedia, the free encyclopedia
ARM Cortex-A8
Designed byARM Holdings
Common manufacturer(s)
Instruction setARMv7
L1 cache32 KiB/32 KiB
L2 cache512 KiB

The ARM Cortex-A8 is a processor core designed by ARM Holdings implementing the ARM v7 (32-bitinstruction set architecture.

Compared to the ARM11 core, the Cortex-A8 is a dual-issue superscalar design, achieving roughly twice the instructions executed per clock cycle. The Cortex-A8 was the first Cortex design to be adopted on a large scale for use in consumer devices.[1]

Key features of the Cortex-A8 core are:

  • Frequency from 600 MHz to 1 GHz and above
  • Superscalar dual-issue microarchitecture
  • NEON SIMD instruction set extension [2]
  • VFPv3 Floating Point Unit
  • Thumb-2 instruction set encoding
  • Jazelle RCT (Also known as ThumbEE instruction set)
  • Advanced branch prediction unit with >95% accuracy
  • Integrated level 2 Cache (0–4 MiB)
  • 2.0 DMIPS/MHz




Several system-on-chips (SoC) have implemented the Cortex-A8 core, including:

ARM Cortex-A9 MPCore

From Wikipedia, the free encyclopedia
ARM Cortex-A9 MPCore
Designed byARM Holdings
Common manufacturer(s)
  • TSMC
    Samsung Electronics
Max. CPU clock rate0.8 GHz  to 2 GHz 
Instruction setARMv7
L1 cache32 KB I, 32 KB D
L2 cache128 KB–8 MB (configurable with L2 cache controller)

The ARM Cortex-A9 MPCore is a 32-bit multicore processor providing up to 4 cache-coherent Cortex-A9 cores, each implementing the ARM v7 instruction set architecture.[1]




Key features of the Cortex-A9 core are:[2]

  • Out-of-order speculative issue superscalar execution pipeline giving 2.50 DMIPS/MHz/core.
  • NEON SIMD instruction set extension performing up to 16 operations per instruction (optional).
  • High performance VFPv3 floating point unit doubling the performance of previous ARM FPUs (optional).
  • Thumb-2 instruction set encoding reduces the size of programs with little impact on performance.
  • TrustZone security extensions.
  • Jazelle DBX support for Java execution.
  • Jazelle RCT for JIT compilation.
  • Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution.
  • L2 cache controller (0-4 MB).
  • Multi-core processing.

ARM states that the TSMC 40G hard macro implementation typically operating at 2 GHz; a single core (excluding caches) occupies less than 1.5 mm2 when designed in a TSMC 65 nanometer (nm) generic process[3] and can be clocked at speeds over 1 GHz, consuming less than 250 mW per core.[4]


Several system on a chip (SoC) devices implement the Cortex-A9 core, including:

Systems on a chip[edit]

DeveloperNameCoresProcessNEONSIMDVector floating point unitGPU
AlteraSoC FPGA
1-228 nmYesVFPv3optionally implemented in FPGA; TES Electronic Solutions D/AVE HD
165 nmYesVFPv3ARM Mali-400
AMLogicAML8726-MX240 nmYesVFPv3ARM Mali-400 MP2
AMLogicAML8726-M8428 nmYesVFPv3ARM Mali-450 MP6
Apple Inc.A5232 nm
45 nm
YesVFPv3PowerVR SGX543MP2
Apple Inc.A5X245 nmYesVFPv3PowerVR SGX543MP4
BroadcomBCM11311 (Persona ICE)240 nm??Broadcom Videocore IV
BroadcomBCM21654G140 nmYesVFPv3Broadcom Videocore IV
BroadcomBCM21664T240 nmYesVFPv3Broadcom Videocore IV
CalxedaEnergyCore ECX-1000[8]440 nmYesVFPv3-
Freescale Semiconductori.MX6[28]1-440 nmYesVFPv3-D16Vivante Corporation GPU IP cores[29]
HiSiliconK3V2 (Hi3620)440 nmYesVFPv3Vivante GC4000
LG CorpLG L92???ARM Mali-400 MP4
MarvellPXA986245 nmYesVFPv3PowerVR SGX540 / Vivante GC1000 (Galaxy Tab 3 7-inch)
MarvellPXA988245 nmYesVFPv3?
MediaTekMT6575140 nmYesVFPv3PowerVR SGX531[15]
MediaTekMT6577240 nmYesVFPv3PowerVR SGX531[16]
NufrontNuSmartTM 2816(NS2816)2?YesVFPv3ARM Mali-400[30]
NufrontNuSmartTM 2816M (NS2816M)2?YesVFPv3ARM Mali-400
NufrontNuSmartTM 115 (NS115)2?YesVFPv3ARM Mali-400
NvidiaTegra 2 series240 nmNoVFPv3-D16GeForce ULP
NvidiaTegra 3 (Kal-El) series440 nmYesVFPv3GeForce ULP
Renesas ElectronicsEMMA Mobile/EV2[31]??Yes?PowerVR SGX530
RockchipRK2928140 nm??ARM Mali-400
RockchipRK3066[20]240 nmYesVFPv3ARM Mali-400 MP4
RockchipRK31282?YesVFPv3ARM Mali-400 MP4
RockchipRK3188[32]428 nmYesVFPv3ARM Mali-400 MP4
SamsungExynos 4 Dual245 nmYesVFPv3ARM Mali-400 MP4
SamsungExynos 4 Dual232 nmYesVFPv3ARM Mali-400 MP4
SamsungExynos 4 Quad432 nmYesVFPv3ARM Mali-400 MP4
STMicroelectronicsSPEAr1340??NoVFPv3ARM Mali-200[33]
ST-EricssonNova A9500245 nmYesVFPv3ARM Mali-400
ST-EricssonNovaThor U8500245 nmYesVFPv3ARM Mali-400
ST-EricssonNovaThor U9500245 nmYesVFPv3ARM Mali-400
SonyPlayStation Vita440 nmYesVFPv3PowerVR SGX543MP4+
Texas InstrumentsOMAP4430
245 nmYesVFPv3PowerVR SGX540
Texas InstrumentsOMAP4470245 nmYesVFPv3PowerVR SGX544
Trident MicrosystemsPNX8473[34]1???PowerVR SGX531
Trident MicrosystemsPNX8483[35]1???PowerVR SGX531
Trident MicrosystemsPNX8491[36][dead link]1???PowerVR SGX531
WonderMediaWM88501?Yes?ARM Mali-400
WonderMediaWM8880240 nm??ARM Mali-400 MP2
WonderMediaWM89501???ARM Mali-400[25]
WonderMediaWM8980240 nm??ARM Mali-400 MP2
XilinxZynq-7000[37]?28 nmYesVFPv3
??YesVFPv3ZiiLABS flexible Stemcell media processing

Development platforms[edit]

Origenboard[38]Samsung Exynos 42101 GiB DDR3-2 Port SD/MMC Card Slot-embedded-SWB-A31SWB-A31-----
Odroid-X[39]Samsung Exynos 44121 GiB LP-DDR2 800-SDHC Card Slot + eMMC module socket-6*USB2.0 host + µUSB2.0 device10/100 Mb-------
PandaBoardPandaBoardTI OMAP4430[40]1 GiB LP-DDR2-Full size SD/MMC card-LAN9514-JZXLAN9514-JZXLS240-WI-01-A20LS240-WI-01-A20-----
Calao systemsSnowball[41]ST-Ericsson Nova A9500[42]1 GiB LP-DDR24 / 8GB e-MMCmicroSD-FT232RLAN9221AW-NH580AW-NH580AW-NH580LSM303DLHLSM303DLHL3G4200DLPS001WP
Trim-SliceTrim-Slice[43]Tegra 2 series1 GiB DDR2-667-Full size SD slot (SDHC) + microSD slot (SDHC)GL830embeddedRTL8111DLRT3070------
Radxa Rock[44]Rockchip RK31882 GiB DDR3 8008GB Nand FlashmicroSD (SDXC)-2*USB2.0 host + µUSB2.0 device10/100 Mb150Mbps 802.11b/g/nBluetooth 4.0-----

ARM Cortex-A5

From Wikipedia, the free encyclopedia
ARM Cortex-A5
Designed byARM Holdings
Common manufacturer(s)
Instruction setARMv7
L1 cache4-64 KB/4-64 KB

The ARM Cortex-A5 is a processor core designed by ARM Holdings implementing the ARM v7 instruction set architecture.




It is intended to replace the ARM9 and ARM11 cores for use in low-end devices.[1] Compared to those older cores, the Cortex-A5 offers the advanced features of the ARM v7 architecture over the v4/v5 (ARM9) and v6 (ARM11) architectures e.g VFPv4 and NEON advanced SIMD. It also allows devices to run current software, which is increasingly focusing on ARM v7 and dropping support for earlier architectures.

Key features of the Cortex-A5 core are:


Several system-on-chips (SoC) have implemented the Cortex-A5 core, including:

ARM Cortex-A7 MPCore

From Wikipedia, the free encyclopedia
ARM Cortex-A7 MPCore
Designed byARM Holdings
Instruction setARMv7
L1 cache8-64 KB/8-64 KB
L2 cacheOptional, up to 1 MB

The ARM Cortex-A7 MPCore is a processor core designed by ARM Holdings implementing the ARM v7 instruction set architecture.




It has two target applications; firstly as a smaller, faster, and more power-efficient successor to the Cortex-A8. The other use is in the big.LITTLEarchitecture, combining one or more A7 cores with one or more Cortex-A15 cores into a heterogeneous system.[1] To do this it is fully feature-compatible with the A15.

Key features of the Cortex-A7 core are:


Several system-on-chips (SoC) have implemented the Cortex-A7 core, including:

ARM Cortex-A12

From Wikipedia, the free encyclopedia
ARM Cortex-A12
Designed byARM Holdings
Instruction setARMv7
L1 cache32-64 KiB I, 32 KiB D
L2 cache256 KiB–8 MiB (configurable with L2 cache controller)

The ARM Cortex-A12 is a 32-bit multicore processor that has been designed to be the successor to the Cortex-A9. It provides up to 4 cache-coherent cores, each implementing the ARM v7 instruction set architecture.[1]




ARM claims that the Cortex-A12 core is 40 percent more powerful than the Cortex-A9 core.[2] New features not found in the Cortex-A9 include hardware virtualization and 40-bit Large Physical Address Extensions (LPAE) addressing. The CPU can also be used in a big.LITTLE solution together with the Cortex-A7 processor.[3]

Key features of the Cortex-A12 core are:[4]

ARM Cortex-A15

From Wikipedia, the free encyclopedia
  (Redirected from  ARM Cortex-A15 MPCore)
ARM Cortex-A15 MPCore
Arm 5250 full 1.jpg
ProducedIn production late 2011,[1]to market late 2012[2]
Designed byARM
Max. CPUclock rate1.0 GHz  to 2.5 GHz 
Min. feature size32 nm/28 nm initially[3] to22 nm roadmap[3]
Instruction setARMv7
Cores1–4 per cluster, 1–2 clusters per physical chip[4]
L1 cache64 KB (32 KB I-cache, 32 KB D-cache) per core
L2 cacheUp to 4 MB[5] per cluster
L3 cachenone

The ARM Cortex-A15 MPCore is a multicore ARM architecture processor providing an out-of-order superscalar pipeline ARM v7 instruction set running at up to 2.5 GHz.[6]




ARM has claimed that the Cortex A15 core is 40 percent more powerful than the Cortex-A9 core with the same number of cores at the same speed.[7] The first A15 designs came out in the autumn of 2011, but products based on the chip did not reach the market until 2012.[1]

Key features of the Cortex-A15 core are:

  • 40-bit Large Physical Address Extensions (LPAE) addressing up to 1 TB of RAM.[8][9] As per the x86 Physical Address Extension, still only 32-bit address space is available per process.[10]
  • 15 stage integer/17–25 stage floating point pipeline, with out-of-order speculative issue 3-way superscalarexecution pipeline[11]
  • 4 cores per cluster, up to 2 clusters per chip with CoreLink 400 (an AMBA-4 coherent interconnect). ARM provides specifications but the licencees individually design ARM chips, and AMBA-4 scales beyond 2 clusters.
  • DSP and NEON SIMD extensions onboard (per core)
  • VFPv4 Floating Point Unit onboard (per core)
  • Hardware virtualization support
  • Thumb-2 instruction set encoding reduces the size of programs with little impact on performance.
  • TrustZone security extensions
  • Jazelle RCT for JIT compilation
  • Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution
  • 32 KB data + 32 KB instruction L1 cache per core
  • Integrated low-latency level-2 cache controller, up to 4 MB per cluster


First implementation came from Samsung in 2012 with the Exynos 5 Dual, which shipped in October 2012 with the Samsung Chromebook Series 3 (ARM version), followed in November by the Google Nexus 10.

Implementations of other manufacturers are expected to hit market in 2013.

Press announcements of forthcoming implementations:

Other licensees, such as LG,[19][20] are expected to produce an A15 based design at some point.

Systems on a chip[edit]

Model NumberSemiconductor technologyCPUGPUMemory interfaceWireless radio technologiesAvailabilityUtilizing devices
HiSilicon K3V328 nm HPLbig.LITTLE architecture using
1.8 GHz dual-core ARM Cortex-A15
+ dual-core ARM Cortex-A7
Mali-T658  H2 2013 
Nvidia Tegra 4 T4028 nm HPL1.9 GHz quad-core ARM Cortex-A15[21] + 1 low power coreNvidia GeForce @ 72 core, 672 MHz, 96.8 GFLOPS = 48 PS + 24 VU × 0.672 × 2 (96.8 GFLOPS)[22](support DirectX 11+,OpenGL 4.X, and PhysX)32-bit dual-channel DDR3L or LPDDR3 up to 933 MHz (1866 MHz data rate)[21]Category 3 (100 Mbit/s) LTEQ2 2013Nvidia Shield

Tegra Note 7

Nvidia Tegra 4 AP4028 nm HPL1.2-1.8 GHz quad-core + low power coreNvidia GPU 60 [21] cores (supportDirectX 11+, OpenGL 4.X, and PhysX)32-bit dual-channel800 MHz LPDDR3Category 3 (100 Mbit/s) LTEQ3 2013 
Samsung Exynos5 Dual32 nm HKMG1.7 GHz dual-coreARM Mali-T604 (quad-core)32-bit dual-channel800 MHz LPDDR3/DDR3or 533 MHz LPDDR2 Q3 2012Arndale Board,Chromebook,Nexus 10, Armbrix Board
Exynos 5 Octa[23][24][25]
(Internally Exynos 5410)
28 nm HKMG1.6–1.8 GHz quad-core ARM Cortex-A15 and 1.2 GHz quad-core ARM Cortex-A7PowerVR SGX544MP3 @ 533 MHz32-bit dual-channel800 MHz LPDDR3 Q2 2013Samsung Galaxy S4,


Samsung Exynos5 Octa[26]
(Internally Exynos 5420)
28 nm HKMG1.8-1.9 GHz quad-core ARM Cortex-A15 and 1.3 GHz quad-core ARM Cortex-A7(ARM big.LITTLE)ARM Mali-T628 MP6 @ 600 MHz; 115.2 GFLOPS = 16FP x 2 Vec4 x 6 x 0.600 (115.2 GFLOPS)(?)32-bit Dual-channel 933 MHz LPDDR3e (14.9 GB/sec) Q3 2013Samsung Galaxy Note 3
Texas InstrumentsOMAP543028 nm2.0 GHz dual-corePowerVR SGX544MP2 @ 532 MHz + dedicated 2D graphics accelerator32-bit dual-channel532 MHz LPDDR2 Q2 2013 
Texas InstrumentsOMAP543228 nm2.0 GHz dual-corePowerVR SGX544MP2 @ 532 MHz + dedicated 2D graphics accelerator32-bit dual-channel532 MHz DDR3 Q2 2013


From Wikipedia, the free encyclopedia

ARM big.LITTLE is a heterogeneous computing architecture developed by ARM Holdings coupling (relatively) slower, low-power processor cores with (relatively) more powerful and power-hungry ones. The intention being to create a multi-core processor that can adjust better to dynamic computing needs and use less power than clock scaling alone. In October 2011, big.LITTLE was announced along with the Cortex-A7, which was designed to be architecturally compatible with theCortex-A15.[1] In October 2012 ARM announced the Cortex-A53 and Cortex-A57 (ARMv8-A) cores, which are also compatible with each other to allow their use in a big.LITTLE chip.[2]



Cluster migration[edit]

There are three ways[3] for the different processor cores to be arranged in a big.LITTLE design, depending on the scheduler implemented in the Linux kernel.[4]The clustered model approach is the first and simplest implementation. With this approach the operating system scheduler can only see one of the two processor clusters, when the load on one cluster hits a certain point, the system transitions to the other cluster. All relevant data is passed through the common L2 cache, the first core cluster is powered off and the other one is activated. A Cache Coherent Interconnect (CCI) is used. This model has been implemented in theSamsung Exynos 5 Octa (5410)[5]

In-kernel switcher (CPU migration)[edit]


CPU migration via the in-kernel switcher (IKS) involves pairing up a 'big' core with a 'LITTLE' core, with possibly many identical pairs in one chip. Each pair operates as one virtual core, and only one real core is (fully) powered up and running at a time. The 'big' core is used when demand is high, the 'LITTLE' core when demand is low. When demand on the virtual core changes (between high and low), the incoming core is powered up, running state is transferred, the outgoing is shut down, and processing continues on the new core. Switching is done via the cpufreq framework. A complete big.LITTLE IKS implementation is expected in Linux 3.11 or 3.12. big.LITTLE IKS is an improvement of Cluster Migration, the main difference is that each pair is visible to the scheduler.

The more complex arrangement involves a non-symmetric grouping of 'big' and 'LITTLE' cores. A single chip could have one or two 'big' cores and many more 'LITTLE' cores, or vice-versa. Nvidia created something similar to this with the low-power 'companion core' in their Tegra 3 SoC.

Heterogeneous multi-processing (global task scheduling)[edit]


The most powerful use model of big.LITTLE is heterogeneous multi-processing (MP), which enables the use of all physical cores at the same time. Threads with high priority or computational intensity can in this case be allocated to the 'big' cores while threads with less priority or less computational intensity, such as background tasks, can be performed by the 'LITTLE' cores.[6] Upstream big.LITTLE GTS patches are expected to be fully incorporated into the mainline Linux kernel in a few quarters. This model has been implemented in theSamsung Exynos 5 Octa (5420)[7]


The paired arrangement allows for switching to be done transparently to the operating system using the existing dynamic voltage and frequency switching (DVFS) facility. The existing DVFS support in the kernel (e.g. cpufreq in Linux) will simply see a list of frequencies/voltages and will switch between them as it sees fit, just like it does on existing hardware. However, the low-end slots will activate the 'LITTLE' core and the high-end slots will activate the 'big' core.

Alternatively, all cores may be exposed to the kernel scheduler, which will decide where each process/thread is executed. This will be required for the non-paired arrangement but could possibly also be used on paired cores. It poses unique problems for the kernel scheduler, which, at least with modern commodity hardware, has been able to assume all cores in a SMP system are equal.

Advantages of global task scheduling[edit]

  • Finer-grained control of workloads that are migrated between cores. Because the scheduler is directly migrating tasks between cores, kernel overhead is reduced and power savings can be correspondingly increased.
  • Implementation in the scheduler also makes switching decisions faster than in the cpufreq framework implemented in IKS.
  • The ability to easily support non-symmetrical SoCs (e.g. with 2 Cortex-A15 cores and 4 Cortex-A7 cores).
  • The ability to use all cores simultaneously to provide improved peak performance throughput of the SoC compared to IKS.


SoCSemiconductor technologybig coresLITTLE coresGPUMemory interfaceWireless radio technologiesAvailabilityDevices
HiSilicon K3V328 nm1.8 GHz dual-coreCortex-A151.2 GHz dual-core Cortex-A7Mali-T658  H2 2013 
Samsung Exynos 5 Octa (5410 model)[8][9]28 nm1.6-1.8 GHz quad-core Cortex-A151.2 GHz quad-core Cortex-A7PowerVR SGX544MP332-bit dual-channel 800 MHz LPDDR3 (12.8 GB/sec) Q2 2013Exynos 5-basedSamsung Galaxy S4
Samsung Exynos 5 Octa (5420 model)[10]28 nm1.8-2.0 GHz quad-core Cortex-A151.3 GHz quad-core Cortex-A7Mali-T628MP632-bit dual-channel 933 MHz LPDDR3e (14.9 GB/sec) Q4 2013Exynos 5-basedSamsung Galaxy Note 3
Renesas Mobile MP6530[11]28 nm2 GHz dual-core Cortex-A151 GHz dual-core Cortex-A7PowerVR SGX544Dual-channel LPDDR3LTE CAT4


2014-02-11 14:55:14  7529 次阅读  稿源:cnBeta.COM  18 条评论


首先,是最小的Cortex-A7。该核心具有非常低的功耗要求,而ARM甚至还发布了基于A7的变种——Cortex-A53——并且兼容64位的ARM v8指令集架构。








除了Cortex-A17,ARM还宣布了新的视频处理器(Mali-V500)、以及新的显示控制器(Mali-DP500)。这些模块主要面向采用了Mali-T720 GPU的中端SoC。该显示控制器支持ARM的AFBC帧缓冲压缩技术,有点cross-IP集成协同的意味。








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