基于stm32单片机外文文献_单片机外文文献

A Flexible and Parameterized Architecture

for Multicore Microcontroller

Cesar Giacomini Penteado

University of Sao Paulo (LSITEC), Sao Paulo, Brazil

Email: cesargiacomini@gmail.com

Sergio Takeo Kofuji and Edward David Moreno

University of Sao Paulo(POLI, Sao Paulo, Brazil) and Federal University of Sergipe (DCOMP-UFS), Aracaju, Brazil

Email: kofuji@lsi.usp.br, edwdavid@gmail.com

Abstract

—This paper presents the concept and preliminary

tests

in

FPGA

of

a

specific

architecture

for

a

flexible

multicore

microcontroller.

It

is

aimed

to

intermediate

complexity

embedded

applications.

A

previous

exact

characterize

of

the

microcontroller

model

and

its

target

applications is a costly-time task,

and it depends

mostly on

experience

of

the

engineers

and

programmers.

The

proposed

architecture

can

aid

the

development

of

new

applications, for selecting resources during the development

phase.

We

have

designed

a

prototype

in

FPGA

which

is

working and running applications with up seven CPUs.

Index

Terms

Multicore,

Microcontroller,

Embedded,

FPGA, soft processor, VHDL

I.

I

NTRODUCTION

Advances in researches and digital systems technology

have

enabled

the

joint

of

computational

power

from

several

intercommunicative

processors

in

the

same

package.

The

multicore

concept

arises,

a

processor

compounded

by

identical

and

functional

copies

of

a

processor or several distinct functional units [1].

The

Multicore

microcontrollers

concept

appears

with

the

joint

of

several

processors

in

a

same

chip,

and

each

processor

supported

by

some

peripherals.

Multicore

microcontrollers start being available in the market.

There

are

several

microcontroller

chip

vendors

and

each

one

of

these

avail

a

wide

variety

of

models

with

each

time

more

specific

characteristics.

Thus,

aiming

to

achieve

the

different

demands

by

project

requirements,

each

vendor avails several product lines, and then,

from

each of these lines, several microcontroller models. These

models vary from simple MCUs with 8bit processors and

few simple peripherals to sophisticated MCUs with 32bit

processors and several robust peripherals.

In between the simple MCUs and robust MCUs there

is a great variety of microcontroller models with different

peripheral

numbers

and

peripheral

settings

around

the

CPU.

Then

these

microcontrollers

are

classified,

in

this

work, as "medium MCUs".

The

medium

MCUs

are

mostly

used

in

embedded

applications

and

often

its

resources

are

not

fully

used,

because,

a

previous

exact

characterize

of

the

microcontroller

model

and

its

target

applications

is

a

costly-time

task.

In

some

concluded

applications

some

resources

and

peripherals

are

never

used

because

the

peripherals have specific and static behavior.

For

example,

in

a

design

which

a

USB

peripheral

is

required,

two

chips

can

be

used:

the

STM32F103VF,

from

STmicroelectronics,

and

the

PIC24HJ128GP510A,

from

Microchip.

Both

also

have

several

Timers,

PWM,

I2C,

etc.,

which

are

not

needed

in

the

example.

These

unneeded peripherals can not be used to other functions.

There is no flexibility.

In

this

work,

the

concept

of

a

scalable,

flexible

and

parameterized architecture is showed and it can result in a

customized

microcontroller

containing

the

minimum

number of resources to the application in development.

The proposed architecture can support in the previous

characterization of the necessary requirements and can be

used

as

an

alternative

in

several

applications.

These

applications are the ones that need a superior processing

for those simple microcontrollers. It happens in a similar

way

to

the

inferior

processing

for

those

robust

microcontrollers.

The

proposed

architecture

is

called

FePAMM

-

Flexible

and

Parameterized

Architecture

for

Multicore

Microcontroller,

and

it

aimed

to

medium

complexity

embedded

applications.

We

like

to

highlight

the

main

contributions of our architecture:

-

An

architecture

composed

by

interconnected

minimalist

processors.

These

processors

perform

control

functions,

data

reception

and

generation,

and

are

capable

to

emulate

functions

of

specific

peripherals.

This

architecture

is

flexible

and

allows

creating

distinct

and

dedicated

functions

in

each

processor.

-

We have done an approach for the message exchange

that

allows

processor's

synchronization

in

a

simple

way.

So,

the

messages

can

be

independently

sent

or

receive,

at

any

time

for

any

processor

of

the

microcontroller multicore. Therefore, the transmission

of many synchronous messages is allowed.

-

On

the

other

side,

we

have

created

an

approach

to

obtain redundancy of the processing in a simple way,

which

take

advantages

of

swap

among

synchronous

messages.

Each

processor

has

its

own

program

memory,

RAM

memory

and

independent

ways

for

communicating

to

others

processors.

Thus,

our

JOURNAL OF COMPUTERS, VOL. 6, NO. 11, NOVEMBER 2011

2277

© 2011 ACADEMY PUBLISHER

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