新code为aadb010476_VHDL新手求助，看一下这个code哪里错了？

libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;----Uncommentthefollowinglibrarydeclarationifinstantiating----anyXilinxp...

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity comb is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : in STD_LOGIC_VECTOR (3 downto 0);

c : in STD_LOGIC_VECTOR (3 downto 0);

d : in STD_LOGIC_VECTOR (3 downto 0);

y : out STD_LOGIC_VECTOR (4 downto 0);

opcode : in STD_LOGIC_VECTOR (2 downto 0);

zero : out STD_LOGIC;

carry : out STD_LOGIC;

negative : out STD_LOGIC;

overflow : out STD_LOGIC);

end comb;

architecture Behavioral of comb is

begin

alu: process(a,b,c,d)

variable temp:std_logic_vector(4 downto 0)

begin

case opcode is

when "000" => y <= a + d

if y='0000' then

zero <= '1';

Elsif temp(4)= 1 then

carry <= '1'

overflow <= '1'

end if

when "001"=> y <= c-a

if y='0000' then

zero<='1';

Elsif temp(4)=1 then

carry<= '1'

overflow<= '1'

negative<= '1'

end if

when "010"=> y <= a and b and c

if y='0000' then

zero<='1';

end if

when "011"=> y <= a or d

if y='0000' then

zero<='1';

end if

when "100"=> y <= NOT a

if y='0000' then

zero<='1';

end if

when others => y <= '0000'

end case

end process alu

end Behavioral;

用xilin检查之后它就说

ERROR:HDLParsers:164 - "D:/Profiles/11081611/Desktop/adsass1/comb.vhd" Line 47. parse error, unexpected TOKBEGIN, expecting AFFECT or SEMICOLON

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