【SDK】控制PL侧GPIO

 将PL侧的4个IO设置成gpio口，调用axi-gpio模块。

vivado搭建原理图：zynq <-> AXI_Interconnect <-> AXI_GPIO <-> gpio[3:0]

设置约束

# B34_0  R19 CS
# B34_25 T19 SO input
# B35_0  G14 SCLK
# B35_25 J15 SI
set_property PACKAGE_PIN R19 [get_ports {gpio_tri_io[3]}]
set_property PACKAGE_PIN T19 [get_ports {gpio_tri_io[2]}]
set_property PACKAGE_PIN G14 [get_ports {gpio_tri_io[1]}]
set_property PACKAGE_PIN J15 [get_ports {gpio_tri_io[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {gpio_tri_io[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_tri_io[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_tri_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gpio_tri_io[0]}]

寄存器地址

u32 *pGpioNor  = (u32 *)XPAR_AXI_GPIO_0_BASEADDR;
/* gpio */
u32 *pGpioData = (u32 *)0x41200000;
u32 *pGpioMode = (u32 *)0x41200004;

设置in/out和data

/* GPIO read ID */
*pGpioMode = 0x04;// [3]input
*pGpioData = 0x00;// output 0

 

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转载于:https://www.cnblogs.com/kevinchase/p/7099906.html