实验现象:
通过仿真波形,分析输入与输出的关系,可以清晰的看到所添加信号波形的变化与程序所写的一致。
核心代码:
module modelsim( input CLK_12M, output FPGA_LEDR ); //-------------------------rst_n-----------------------// reg [3:0]cnt_rst = 4'd0; reg rst_n = 1'd0; always@(posedge CLK_12M) //产生复位信号 begin if(cnt_rst==4'd10) begin rst_n <= 1'd1; cnt_rst <=4'd10 ; end else cnt_rst <= cnt_rst +1'd1; end //-----------------------led---------------------------// reg [6:0]cnt_led ; reg led; always@(posedge CLK_12M or negedge rst_n) begin if(!rst_n) begin cnt_led <= 7'd0; led <= 1'd1; end else if(cnt_led==7'd100) begin cnt_led <= 7'd0; led <= ~led; end else cnt_led <= cnt_led + 1'd1; end assign FPGA_LEDR = led;//LED以极快速度闪烁,肉眼看为常亮 //---------------------emdmodule-----------------------// endmodule
实验方法及指导书:
链接:http://pan.baidu.com/s/1kVCBkWn 密码:vv0i