Features
LoRa™ Modem
168 dB maximum link budget
+20 dBm - 100 mW constant RF output vs. V supply
+14 dBm high efficiency PA
Programmable bit rate up to 300 kbps
High sensitivity: down to -148 dBm
Bullet-proof front end: IIP3 = -11 dBm
Excellent blocking immunity
Low RX current of 9.9 mA, 200 nA register retention
Fully integrated synthesizer with a resolution of 61 Hz
FSK, GFSK, MSK, GMSK, LoRaTMand OOK modulation
Built-in bit synchronizer for clock recovery
Preamble detection
127 dB Dynamic Range RSSI
Automatic RF Sense and CAD with ultra-fast AFC
Packet engine up to 256 bytes with CRC
Built-in temperature sensor and low battery indicator
mark:
clear FIFO data buffer
1. 切换到 RX mode
2. 进入到 sleep mode (丢失buffer中存储的数据)
FIFO data buffer 中数据时不会被清除的(除非上诉情况),“擦除”只能是写入新的数据到当前占用的内存(FIFO data buffer)
FIFO data buffer 中读写数据通过SPI定义RegFifoAddrPtr (指针),所以使用前需要赋初值
在读或写作的FIFO数据缓冲区(RegFifo)地址指针将自动增加
FIFO data buffer 接收时即使CRC错误,buffer也不清零,如果接收时长度超过设置的上限(RegRxNbBytes) 会重新覆盖(RegFifoRxBaseAddr )