MPC750UM-MMU阅读笔记

7.3.8 MMU Instructions and Register Summary

The MMU instructions and registers allow the operating system to set up the SRs. Additionally, the operating system has the resources to set up the block address translation areas and the page tables in memory.

MMU指令和寄存器允许操作系统设置这些SR寄存器。另外，操作系统有资源设置内存中块地址转换区域与页表。

Note that because the implementation of TLBs is optional, instructions that refer to TLBs are also optional. However, because TLBs serve as caches of the page table, there must be a software protocol for maintaining coherency between these caches and the tables in memory whenever the tables in memory are modified. Therefore, the OEA specifies that a processor implementing a TLB is guaranteed to have a means for doing the following:

• Invalidating an individual TLB entry

• Invalidating the entire TLB

注意，由于TLB的实现是可选的，因此关于TLB的指令也是可选的。但是，由于TLB用作页表的缓存，因此必须有软件协议来保持缓存与内存中的页表的相关性。因此，OEA规定，实现TLB的处理器保证具有执行以下操作的方法：

•使单个TLB条目无效
•使整个TLB失效

 

Figure 7-5 shows the registers that the operating system uses to program the MMU. These registers are accessible to supervisor-level software only (supervisor level is referred to as privileged state in the architecture specification).

下图现实了操作系统用于为MMU编程的寄存器。这些寄存器是仅可访问内核级软件。

7.3.9 TLB Entry Invalidation

Optionally, processors implement TLB structures that store on-chip copies of those PTEs that are resident in physical memory. Such processors can use tlbie and tlbia instructions to invalidate resident TLB entries. These instructions may also enable a TLB invalidate signalling mechanism in hardware so that other processors also invalidate their resident copies of the matching PTE. See Chapter 8, “Instruction Set,” for detailed information about tlbie and tlbia.

7.5 Block Address Translation

The block address translation (BAT) mechanism in the OEA provides a way to map ranges of effective addresses larger than a single page into contiguous areas of physical memory. Such areas can be used for data that is not subject to normal virtual memory handling (paging), such as a memory-mapped display buffer or an extremely large array of numbers. The following sections describe the implementation of block address translation, including the block protection mechanism, followed by a block translation summary with a detailed flow diagram.

OEA中的块地址转换（BAT）机制提供了一种将大于单页的有效地址范围映射到物理内存的连续区域的方法。这些区域可用于不受正常虚拟内存处理（分页）约束的数据，例如内存映射显示缓冲区或非常大的数字数组。以下各节描述了块地址转换的实现，包括块保护机制，然后是块转换摘要和详细的流程图。

 

The block address translation mechanism is implemented as a software-controlled BAT array, which maintains the address translation information for eight blocks of memory. The BAT array is maintained by the system software and is implemented as a set of 16 supervisor-level SPRs. Each block is defined by a pair of SPRs called upper and lower BAT registers, which contain the effective and physical addresses for the block.

块地址转换机制作为一个软件控制的BAT数组来实现，它为八个内存块维护地址转换信息。BAT阵列由系统软件维护，并作为一组16个主管级SPR实现。每个块由一对称为上下BAT寄存器的SPR定义，其中包含块的有效地址和物理地址。

 

 

shows the organization of the BAT array. Four pairs of BAT registers are provided for translating instruction addresses and four pairs of BAT registers are used for translating data addresses. These eight pairs of BAT registers comprise two four-entry fully-associative BAT arrays (each BAT array entry corresponds to a pair of BAT registers). The BAT array is fully-associative in that any address can reside in any BAT. In addition, the effective address field of all four corresponding entries (instruction or data) is simultaneously compared with the effective address of the access to check for a match.

显示BAT数组的组织。提供四对BAT寄存器用于翻译指令地址，四对BAT寄存器用于翻译数据地址。这八对BAT寄存器包括两个四项全关联BAT数组（每个BAT数组项对应一对BAT寄存器）。BAT数组是完全关联的，因为任何地址都可以驻留在任何BAT中。此外，所有四个相应条目（指令或数据）的有效地址字段同时与访问的有效地址进行比较，以检查是否匹配。

 

Each pair of BAT registers defines the starting address of a block in the effective address space, the size of the block, and the start of the corresponding block in physical address space. If an effective address is within the range defined by a pair of BAT registers, its physical address is defined as the starting physical address of the block plus the low-order effective address bits.

每对BAT寄存器定义有效地址空间中一个块的起始地址、块的大小以及物理地址空间中相应块的起始地址。如果有效地址在一对BAT寄存器定义的范围内，则其物理地址定义为块的起始物理地址加上低阶有效地址位。

Blocks are restricted to a finite set of sizes, from 128 Kbytes (217 bytes) to 256 Mbytes (228 bytes). The starting address of a block in both effective address space and physical address space is defined as a multiple of the block size.

块被限制为一组有限的大小，从128千字节（217字节）到256兆字节（228字节）。在有效地址空间和物理地址空间中，块的起始地址定义为块大小的倍数。

7.6 Memory Segment Model

The OEA divides memory into 256-Mbyte segments. This segmented memory model provides a way to map 4-Kbyte pages of effective addresses to 4-Kbyte pages in physical memory (page address translation), while providing the programming flexibility afforded by a large virtual address space (52 bits). A page address translation may be superseded by a matching block address translation as described in Section 7.5, “Block Address Translation.” If not, the page translation proceeds in the following two steps: 1. From effective address to the virtual address (which never exists as a specific entity but can be considered to be the concatenation of the virtual page number and the byte offset within a page) 2. From virtual address to physical address The page address translation mechanism is described in the following sections, followed by a summary of page address translation with a detailed flow diagram.