一、组合逻辑电路
组合逻辑电路的特点是任意时刻的输出仅取决于输入信号,输入信号变化,输出立刻变化,不依赖时钟
一、与门
1.真值表
Verilog 代码
top.v
module top(a,b,c);
input a;
input b;
output c;
assign c = a & b;
endmodule
top_tb.v
`timescale 1 ns/1 ns
module top_tb();
reg a;
reg b;
wire c;
initial
begin
a = 0;
b = 0;
forever
begin
#({$random}%100)
a = ~a;
#({$random}%100)
b = ~b;
end
end
top t0(.a(a),.b(b),.c(c));
endmodule
Vivado仿真结果
二、或门
2.1真值表
2.2门电路
2.3源代码top.v
module top(a,b,c
);
input a;
input b;
input c;
assign c =a|b;
endmodule
top_tb.v
module top_tb();
reg a;
reg b;
wire c;
initial
begin
a = 0;
b = 0;
forever
begin
#({$random}%100)
a = ~a;
#({$random}%100)
b = ~b;
end
end
top t0(.a(a),.b(b),.c(c));
endmodule
Vivado仿真结果
三、非门
3.1真值表
3.2逻辑电路
3.3代码
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/20 16:11:32
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top(a,b);
input a;
output b;
assign b = ~a;
endmodule
top_tb.v
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/20 16:11:52
// Design Name:
// Module Name: top_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top_tb();
reg a;
wire b;
initial
begin
a = 0;
forever
begin
#({$random}%100)
a = ~a;
end
end
top t0(.a(a),.b(b));
endmodule
四、异或门
异或门的真值表如下,A与B相同时,输出为0。
top.v
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/21 10:11:49
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top(a,b,c);
input a;
input b;
output c;
assign c = a ^ b;
endmodule
top_tb.v
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/21 10:12:56
// Design Name:
// Module Name: top_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top_tb(
);
reg a;
reg b;
wire c;
initial
begin
a = 0;
b = 0;
forever
begin
#({$random}%100)
a = ~a;
#({$random}%100)
b = ~b;
end
end
top t0(.a(a),.b(b),.c(c));
endmodule
五、比较器
比较器真值表
比较器电路图
top.v
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/21 10:42:17
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top(a,b,c
);
input a;
input b;
output c;
assign c = a > b;
endmodule
top_tv.v
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/21 10:43:11
// Design Name:
// Module Name: top_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top_tb(
);
reg a;
reg b;
wire c;
initial
begin
a = 0;
b = 0;
forever
begin
#({$random}%100)
a = ~a;
#({$random}%100)
b = ~b;
end
end
top t0(.a(a),.b(b),.c(c));
endmodule
六、半加器
半加器和全加器是算术运算电路中的而基本单元,由于半加器不考虑从低位来的进位,所以称之为半加器,sum表示相加结果,count表示进位,真值表可表示如下:
半加器电路图
代码top.v
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/21 13:09:32
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top(a,b,sum,count
);
input a;
input b;
output sum;
output count;
assign sum = a ^ b;
assign count = a & b;
endmodule
top_tb.v
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/21 13:11:15
// Design Name:
// Module Name: top_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top_tb(
);
reg a;
reg b;
wire sum;
wire count;
initial
begin
a = 0;
b = 0;
forever
begin
#({$random}%100)
a = ~a;
#({$random}%100)
b = ~b;
end
end
top t0(.a(a),.b(b),.sum(sum),.count(count));
endmodule
七、全加器真值表,全加器需要加上低位来的进位信号,cin真值表如下
代码:top.v
module top(cin,a,b,sum,count
);
input cin;
input a;
input b;
output sum;
output count;
assign {count,sum} = a + b + cin;
endmodule
top_tb.v
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/21 13:29:41
// Design Name:
// Module Name: top_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top_tb(
);
reg a;
reg b;
reg cin;
wire sum;
wire count;
initial
begin
a = 0;
b = 0;
cin = 0;
forever
begin
#({$random}%100)
a = ~a;
#({$random}%100)
b = ~b;
#({$random}%100)
cin = ~cin;
end
end
top t0(.cin(cin),.a(a),.b(b),.sum(sum),.count(count));
endmodule
五、乘法器
乘法的标识很简单,利用"",表示即可,如ab举例如下:
module top(a,b,c);
input [1:0] a;
input [1:0]b;
output [3:0] c;
assign c = a * b;
endmodule
top_tb.v
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/21 13:46:19
// Design Name:
// Module Name: top_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top_tb(
);
reg [1:0] a;
reg [1:0] b;
wire [3:0] c;
initial
begin
a = 0;
b = 0;
forever
begin
#({$random}%100)
a = ~a;
#({$random}%100)
b = ~b;
end
end
top t0(.a(a),.b(b),.c(c));
endmodule
六、数据选择器
在verilog中经常会用到数据选择器,通过选择信号,选择不同的输入信号输出到输出端,如下图真值表,四选一数据选择器,sel[1:0]为选择信号,a,b,c,d为输入信号,Mux为输出信号。
代码top.v
module top(a,b,c,d,sel,Mux
);
input a;
input b;
input c;
input d;
input [1:0]sel;
output reg Mux;
always @(sel or a or b or c or d)
begin
case(sel)
2'b00 : Mux = a;
2'b01 : Mux = b;
2'b10 : Mux = c;
2'b11 : Mux = d;
endcase
end
endmodule
top_tb.v
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/21 14:03:16
// Design Name:
// Module Name: top_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top_tb(
);
reg a;
reg b;
reg c;
reg d;
reg [1:0] sel;
wire Mux;
initial
begin
a = 0;
b = 0;
c = 0;
d = 0;
forever
begin
#({$random%100})
a = {$random%3};
#({$random%100})
b = {$random%3};
#({$random%100})
c = {$random%3};
#({$random%100})
d = {$random%3};
end
end
initial
begin
sel = 2'b00;
#2000 sel = 2'b01;
#2000 sel = 2'b10;
#2000 sel = 2'b11;
end
top t0(.a(a),.b(b),.c(c),.d(d),.sel(sel),.Mux(Mux));
endmodule
七、38译码器
3-8译码器是一个常用的器件,其真值表如下,根据A2,A1,A0的值得出不同的结果。
电路图
top.v
module top(addr,decoder
);
input [2:0]addr;
output reg[7:0] decoder;
always @(addr)
begin
case(addr)
3'b000:decoder = 8'b1111_1110;
3'b001:decoder = 8'b1111_1101;
3'b010:decoder = 8'b1111_1011;
3'b011:decoder = 8'b1111_0111;
3'b100:decoder = 8'b1110_1111;
3'b101:decoder = 8'b1101_1111;
3'b110:decoder = 8'b1011_1111;
3'b111:decoder = 8'b0111_1111;
endcase
end
endmodule
top_tb.v
module top_tb(
);
reg [2:0] addr;
wire [7:0] decoder;
initial
begin
addr = 3'b000;
#20 addr = 3'b001;
#20 addr = 3'b010;
#20 addr = 3'b011;
#20 addr = 3'b100;
#20 addr = 3'b101;
#20 addr = 3'b110;
#20 addr = 3'b111;
end
top t0(.addr(addr),.decoder(decoder));
endmodule
仿真图
八、三态门
在FPGA当中,经常会用到双向IO,需要用到三态门如:bio=en?din:1`bz,en为使能信号,用于打开关闭三态门。电路图如下
top.v
module top(en,din,dout,bio
);
input din;
input en;
output dout;
inout bio;
assign bio = en?din:1'bz;
assign dout = bio;
endmodule
top_tb.v
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2020/11/21 15:11:22
// Design Name:
// Module Name: top_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top_tb(
);
reg en0;
reg din0;
wire dout0;
reg en1;
reg din1;
wire dout1;
wire bio;
initial
begin
din0 = 0;
din1 = 0;
forever
begin
#({$random}%100)
din0 = ~din0;
#({$random}%100)
din1 = ~din1;
end
end
initial
begin
en0 = 0;
en1 = 1;
#100000;
en0 = 1;
en1 = 0;
end
top t0(.en(en0),.din(din0),.dout(dout0),.bio(bio));
top t1(.en(en1),.din(din1),.dout(dout1),.bio(bio));
endmodule