目录
- 寄存器:硬件模块之间交谈的窗口,读出reg状态获取硬件当前的状态,配置reg使其工作在一定模式下
- 通过硬件的reg模型和总线UVC建立一个验证环境
- reg有关的设计流程
- reg model相关类
- 将reg model集成到现有环境,与总线UVC桥接,与dut模型绑定
- reg model常用方法和预定义的seq
- reg测试和功能覆盖率
- reg的域:WO,RO,RW,RC读后擦除clean_on_read,W1S只写一次write_one_to_set
- reg按照地址索引的关系是按字对齐
- 寄存器列表(块):将寄存器按照地址排列
- 寄存器的中心化管理:保证通过软件建立reg模型与硬件reg的内容属性保持一致
uvm_reg
class ctrl_reg extends uvm_reg;
`uvm_object_utils(ctrl_reg)
uvm_reg_field reserved;
rand uvm_reg_field pkt_len;//声明域,且可以随机化
rand uvm_reg_field prio_level;
rand uvm_reg_field chnl_en;
function new(string name ="ctrl_reg");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
virtual function build();
reserved = uvm_reg_field::type_id::create("");
pkt_len = uvm_reg_field::type_id::create("");
prio_level = uvm_reg_field::type_id::create("");
chnl_en = uvm_reg_field::type_id::create("");//例化
reserved.configure(this, 26, 6, "RO", 0, 26'h0, 1, 0 , 0);//配置
pkt_len.configure(this,3,3,"RW",0,3'h0,1,1,0);
prio_level.configure(this,2,1,"RW",0,2'h3,1,1,0);
chnl_en.configure(this,1,0,"RW",0,1'h0,1,1,0);
endfunction
endclass
class stat_reg extends uvm_reg;
`uvm_object_utils()
uvm_reg_field reserved;//保留位的域
rand uvm_reg_field fifo_avail;
function new(string name="stat_reg");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction
virtual function build();
reserved = uvm_reg_field::type_id::create("");
fifo_avail= uvm_reg_field::type_id::create("");
reserved.configure(this,24,8,"RO",0,24'h0,1,0,0);
fifo_avail.configure(this,8,0,"RO",0,8'h0,1,1,0);
endfunction
endclass
class mcdf_rgm extends uvm_reg_block;
`uvm_object_utils(mcdf_rgm)
rand ctrl_reg chnl0_ctrl_reg;
rand ctrl_reg chnl1_ctrl_reg;
rand ctrl_reg chnl2_ctrl_reg;
rand stat_reg chnl0_stat_reg;
rand stat_reg chnl1_stat_reg;
rand stat_reg chnl2_stat_reg;
uvm_reg_map map;
function new(string name ="")
super.new(name, UVM_NO_COVERAGE);
endfunction
virtual function build();
chnl0_ctrl_reg=ctrl_reg::type_id::create("");
chnl0_ctrl_reg.configure(this);//创建,配置,
chnl0_ctrl_reg.build();
chnl1_ctrl_reg=ctrl_reg::type_id::create("");
chnl1_ctrl_reg.configure(this);
chnl1_ctrl_reg.build();
chnl2_ctrl_reg=ctrl_reg::type_id::c