解决方案
What the Clocking Resources Guide is trying to explain in table 2-7 is that these inputs (CE and CLR) should not be connected to signals that change.
If you do connect them to a signal you will receive the following Map warning which lets you know that these will not be used even though you have connected them:
WARNING:PhysDesignRules:1267 - Issue with pin connections and/or configuration on block::.
Useless input. The input pins CE and CLR are not used for BUFR_DIVIDE BYPASS.
The CE and CLR pins should be tied '1' and '0' respectively to avoid both the synthesis error and the Map warning.