tas5424_TAS5424 Datasheet(数据表) 16 Page - Texas Instruments

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Power FETs

Load Diagnostics

OUT1P

OUT1M

V

(OUT1M–OUT1P)

Speaker

Playback

/

Mute

Hi-Z

ChannelSynchronization

Phase1

Phase2

Phase3

Phase4

S2G

100ms

<100ms

S2P

100ms

OL

150ms

SL

150ms

~50ms

~50ms

~50ms

~50ms

~50ms

~50ms

~50ms

~50ms

T0188-01

TAS5414

TAS5424

SLOS514 – FEBRUARY 2007

DESCRIPTION OF OPERATION (continued)

The BTL output for each channel comprises four rugged N-channel 30-V FETs, each of which has an RDSonof

75 m

Ω for high efficiency and maximum power transfer to the load. These FETs are designed to handle large

voltage transients during load dump.

The TAS5414 and TAS5424 incorporate load diagnostic circuitry designed to help pinpoint the nature of output

misconnections during installation. The TAS5414 and the TAS5424 include functions for detecting and

determining the status of output connections. The following diagnostics are supported:

• Short to GND

• Short to PVDD

• Short across load (R < 1 Ω, typical)

• Open load (R > 800 Ω, typical)

• Tweeter detection

The presence of any of the short or open conditions is reported to the system via I2C register read. The tweeter

detect status can be read from the CLIP_OTW pin when properly configured.

1. Output Short and Open Diagnostics—The TAS5414 and TAS5424 contain circuitry designed to detect

shorts and open conditions on the outputs. The load diagnostic function can only be invoked when the

output is in the Hi-Z mode. There are four phases of test during load diagnostics and two levels of test. In

the full level, all channels must be in the Hi-Z state. All four phases are tested on each channel, all four

channels at the same time. When fewer than four channels are in Hi-Z, the reduced level of test is the

only available option. In the reduced level, only short to PVDD and short to GND can be tested. Load

diagnostics can occur at power up before the amplifier is moved out of Hi-Z mode. If the amplifier is

already in play mode, it must Mute and then Hi-Z before the load diagnostic can be performed. By

performing the mute function, the normal pop- and click-free transitions occur before the diagnostics

begin. The diagnostics are performed as shown in Figure 13. Figure 14 shows the impedance ranges for

the open-load and shorted-load diagnostics. The results of the diagnostic are read from the diagnostic

register for each channel via I2C. Note: Do not send a command via I2C to register 0x0C during the load

diagnostic test.

Figure 13. Load Diagnostics Sequence of Events

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