tas5424_TAS5424 Datasheet(数据表) 10 Page - Texas Instruments

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TAS5414

TAS5424

SLOS514A – FEBRUARY 2007 – REVISED JULY 2007

ELECTRICAL CHARACTERISTICS (continued)

Test conditions (unless otherwise noted): TCase= 25°C, PVDD = 14.4 V, RL= 4 Ω, fS= 417 kHz, Rext = 20 kΩ, master mode

operation (see application diagram)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CLIP_OTW signal delay when output

tDELAY_CLIPDET

20

μs

clipping detected

FAULT REPORT

FAULT pin output voltage for logic-level

VOH_FAULT

2.4

high (open-drain logic output)

External 47-k

Ω pullup resistor to 3 V–5.5 V

V

FAULT pin output voltage for logic-level low

VOL_FAULT

0.5

(open-drain logic output)

OPEN/SHORT DIAGNOSTICS

Maximum resistance to detect a short from

RS2P, RS2G

200

Ω

OUT pin(s) to PVDD or ground

Minimum load resistance to detect open

ROPEN_LOAD

Including speaker wires

300

800

1300

Ω

circuit

Maximum load resistance to detect short

RSHORTED_LOAD

Including speaker wires

0.5

1

1.5

Ω

circuit

I2C ADDRESS DECODER

tLATCH_I2CADDR

300

μs

Time delay to latch I2C address after POR

Voltage on I2C_ADDR pin for address 0

Connect to SGND

0%

0%

15%

Voltage on I2C_ADDR pin for address 1

25%

35%

45%

External resistors in series between D_BYP and SGND

VI2C_ADDR

VD_BYP

as a voltage divider

Voltage on I2C_ADDR pin for address 2

55%

65%

75%

Voltage on I2C_ADDR pin for address 3

Connect to D_BYP

85%

100%

100%

I2C

Power-on hold time before I2C

tHOLD_I2C

STANDBY high

1

ms

communication

fSCL

SCL clock frequency

100

kHz

VIH_SCL

SCL pin input voltage for logic-level high

2.1

5.5

V

RPU_I2C= 5-kΩ pullup, supply voltage = 3.3 V or 5 V

VIL_SCL

SCL pin input voltage for logic-level low

–0.5

1.1

V

I2C read, RI2C= 5-kΩ pullup,

VOH_SDA

SDA pin output voltage for logic-level high

2.4

V

supply voltage = 3.3 V or 5 V

VOL_SDA

SDA pin output voltage for logic-level low

0

0.4

V

I2C read, 3-mA sink current

I2C write, RI2C= 5-kΩ pullup,

VIH_SDA

SDA pin input voltage for logic-level high

2.1

5.5

V

supply voltage = 3.3 V or 5 V

I2C write, RI2C= 5-kΩ pullup,

VIL_SDA

SDA pin input voltage for logic-level low

–0.5

1.1

V

supply voltage = 3.3 V or 5 V

Ci

Capacitance for SCL and SDA pins

10

pF

OSCILLATOR

OSC_SYNC pin output voltage for

VOH_OSCSYNC

2.4

3.6

V

logic-level high

I2C_ADDR pin set to MASTER mode

OSC_SYNC pin output voltage for

VOL_OSCSYNC

0.5

V

logic-level low

OSC_SYNC pin input voltage for logic-level

VIH_OSCSYNC

2

3.6

V

high

I2C_ADDR pin set to SLAVE mode

OSC_SYNC pin input voltage for logic-level

VIL_OSCSYNC

0.8

V

low

I2C_ADDR pin set to MASTER mode, fS= 500 kHz,

3.76

4.0

4.24

maximum capacitive loading = 5 pF

I2C_ADDR pin set to MASTER mode, fS= 417 kHz,

fOSC_SYNC

OSC_SYNC pin clock frequency

3.13

3.33

3.63

MHz

maximum capacitive loading = 5 pF

I2C_ADDR pin set to MASTER mode, fS= 357 kHz,

2.68

2.85

3.0

maximum capacitive loading = 5 pF

10

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