modelsim安装_Modelsim10.7安装教程

1. 鼠标右击软件压缩包,选择“解压到modelsim-win64-10.7-se”。

5f309e7f58d7bdee3639ee5f2bac4abc.png

2. 打开解压后的文件夹,鼠标右击“modelsim-win64-10.7-se”,选择“以管理员身份运行”。

50abac29e55cc26cd17a1f781a93400f.png

3. 点击“下一步”。

3c141e60d2e902295c01fe32c6f278ee.png

4. 点击“浏览”选择软件的安装路径(建议安装在C盘以外的其他磁盘,且安装路径不要有中文),点击“下一步”。

93f50c081224aec5ec709a6fc5e09e70.png

5. 点击“同意”。

9d2020847d9437c714ea0b2d2b52cfb6.png

6. 软件正在安装,请耐心等待,谢谢。

7487468deab3f13a2b000a1a7d1ef2ed.png

7. 点击“是‘。

  • 1
    点赞
  • 14
    收藏
    觉得还不错? 一键收藏
  • 0
    评论
Mentor, a Siemens business, has unveiled ModelSim 10.7, is unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment. About Mentor Graphics ModelSim. Modelsim HDL simulator provides FPGA customers with and easy cost-effective way to speed up FPGA development, lab bring up and test. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. Testing in the lab has limited visibility of the signals in design. It can take 8 hours to do a place and route just instrument additional signals or make a small bug fix. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab allowing time spent during lab debug much more productive and focused. In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code. The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).
评论
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值