计算机系统结构习题讲解-0929-重定序
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 存储系统 Answer a. Software is slower because of the overhead of a context switch to the handler code, but the replacement algorithm can be higher than hardware and a wider variety of virtual memory organizations can be readily accommodated.Hardware - faster but less flexible Answer b. Factors affecting on the handling time include: Page table – paged? More efficient page table searching algorithm —— software TLB entry prefetching —— hardware Answer c. Page table structure that change dynamically would be difficult to handle in hardware but possible in software. 存储系统 Adapted from Figure 5.45 Cache misses per 1000 instructions TLB misses per 1000 instr. Program CPI I-Cache L2-Cache I-TLB gcc 0.63 3.43 0.25 0.30 ijpeg 0.49 0.03 0.02 0.10 perl 0.56 1.66 0.09 0.26 swim 0.40 0.00 5.99 0.10 wave5 0.74 0.17 1.72 0.89 hydro2d 0.64 0.01 0.46 0.19 存储系统 Answer d. Program Weight TLB misses/1000 instructions gcc 50% 0.3 perl 25% 0.26 ijpeg 25% 0.10 存储系统 Workload miss rate= ∑Weighti×(TLB misses/1000i)= 50%×0.3+25%×0.26+25%×0.1 = 0.24/1000 instructions Penalty (Hardware)= WMR×TLB miss handling time (10 cycles)= 2.4 cycles/1000 instructions CPI (increase) = 0.0024 clocks/instruction Penalty (Software)= WMR×TLB miss handling time (30 cycles)= 7.2 cycles/1000 instructions CPI (increase)= 0.0072 clocks/instruction 存储系统 Program Weight TLB misses/1000 instructions swim 30% 0.1 wave5 30% 0.89 hydro2d 20% 0.19 gcc 10% 0.3 存储系统 Workload miss rate= ∑Weighti×(TLB misses/1000i)= 30%×0.1+30%×0.89+20%×0.19+10%×0.3 = 0.37/1000 instructions Penalty (Hardware)= WMR×TLB miss handling time (10 cycles)= 3.7 cycles/1000 instructions CPI = 0.0037 clocks/instruction Penalty (Software)= WMR×TLB miss handling time (30 cycles)= 11.1 cycles/1000 instructions CPI = 0.0111 clocks/instruction 存储系统 Answer e.The TLB miss times are too small. Handling a TLB miss requires finding and transferring a page t