j7688_基于MT7688 原厂SDK 使用SPI控制器驱动TFT屏幕ILI9225驱动器(spi接口)

以下是我的一个利用SPI控制器操作屏的一个操作实例 包含一个bpeer_tft.c 和一个bpeer_tft.h

这是我基于flash驱动剥离出来的spi控制器驱动

好的话,顶起来~~~~~~~~~~~~~~~~~~~

下面是代码:

bpeer_tft.c

1 /*

2 * MTD SPI driver for ST M25Pxx flash chips

3 *

4 * Author: Mike Lavender, [email protected]

5 *

6 * Copyright (c) 2005, Intec Automation Inc.

7 *

8 * Some parts are based on lart.c by Abraham Van Der Merwe

9 *

10 * Cleaned up and generalized based on mtd_dataflash.c

11 *

12 * This code is free software; you can redistribute it and/or modify

13 * it under the terms of the GNU General Public License version 2 as

14 * published by the Free Software Foundation.

15 *

16 */

17

18 #include

19 #include

20 #include

21 #include

22 #include

23 #include

24 #include

25 #include

26 #include

27 #include

28 #include

29 #include

30 #include

31 #include

32 #include

33 #include

34 #if defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)

35 #else

36 #include "ralink_spi.h"

37 #endif

38 #include /* O_ACCMODE */

39 #include /* size_t */

40 #include

41

42

43

44

45 #include "bpeer_tft.h"

46

47

48

49

50

51

52

53

54

55

56 //#define SPI_DEBUG

57 #if !defined (SPI_DEBUG)

58 #define ra_inl(addr) (*(volatile unsigned int *)(addr))

59 #define ra_outl(addr, value) (*(volatile unsigned int *)(addr) = (value))

60 #define ra_dbg(args...) do {} while(0)

61 /*#define ra_dbg(args...) do { printk(args); } while(0)*/

62

63 #else

64 #define ra_dbg(args...) do { printk(args); } while(0)

65 #define _ra_inl(addr) (*(volatile unsigned int *)(addr))

66 #define _ra_outl(addr, value) (*(volatile unsigned int *)(addr) = (value))

67

68 u32 ra_inl(u32 addr)

69 {

70 u32 retval = _ra_inl(addr);

71 printk("%s(%x) => %x \n", __func__, addr, retval);

72

73 return retval;

74 }

75

76 u32 ra_outl(u32 addr, u32 val)

77 {

78 _ra_outl(addr, val);

79

80 printk("%s(%x, %x) \n", __func__, addr, val);

81

82 return val;

83 }

84

85 #endif // SPI_DEBUG //

86

87 #define ra_aor(addr, a_mask, o_value) ra_outl(addr, (ra_inl(addr) & (a_mask)) | (o_value))

88 #define ra_and(addr, a_mask) ra_aor(addr, a_mask, 0)

89 #define ra_or(addr, o_value) ra_aor(addr, -1, o_value)

90

91

92

93

94

95

96

97

98

99

100 #define SPI_MAX_DEV 2

101

102 static struct base_spi spi_pre[SPI_MAX_DEV];

103 static struct tft_config_type tft_config[2];

104

105

106

107

108 static int spidrv_major = 111;

109 int eye_l_minor = 0;

110 int eye_r_minor = 1;

111

112

113

114 static struct tft_reg_info tft_reg_data [] = {

115 /* init tft reg */

116 { "rest", 0, 0},

117 { "reg",0x10, 0x0000 }, // Set SAP,DSTB,STB

118 { "reg", 0x11, 0x0000 }, // Set APON,PON,AON,VCI1EN,VC

119 { "reg", 0x12, 0x0000 }, // Set BT,DC1,DC2,DC3

120 { "reg", 0x13, 0x0000 }, // Set GVDD

121 { "reg", 0x14, 0x0000 }, // Set VCOMH/VCOML voltage

122 { "msleep", 40, 0}, //mdelay( 40 }, // Delay 20

123

124 // Please follow this power on sequence

125 { "reg", 0x11, 0x0018 }, // Set APON,PON,AON,VCI1EN,VC

126 { "reg", 0x12, 0x1121 }, // Set BT,DC1,DC2,DC3

127 { "reg", 0x13, 0x0063 }, // Set GVDD

128 { "reg", 0x14, 0x3961 }, // Set VCOMH/VCOML voltage

129 { "reg", 0x10, 0x0800 }, // Set SAP,DSTB,STB

130 { "msleep", 10, 0}, //mdelay( 10 }, // Delay 10 ms

131 { "reg", 0x11, 0x1038 }, // Set APON,PON,AON,VCI1EN,VC

132 { "msleep", 30, 0}, //mdelay( 30 }, // Delay 30 ms

133 { "reg", 0x02, 0x0100 }, // set 1 line inversion

134

135 #if USE_HORIZONTAL//

136 //R01H:SM=0,GS=0,SS=0 (for details,See the datasheet of ILI9225)

137 { "reg", 0x01, 0x001C }, // set the display line number and display direction

138 //R03H:BGR=1,ID0=1,ID1=1,AM=1 (for details,See the datasheet of ILI9225)

139 { "reg", 0x03, 0x1038 }, // set GRAM write direction .

140 #else

141 //R01H:SM=0,GS=0,SS=1 (for details,See the datasheet of ILI9225)

142 { "reg", 0x01, 0x011C }, // set the display line number and display direction

143 //R03H:BGR=1,ID0=1,ID1=1,AM=0 (for details,See the datasheet of ILI9225)

144 { "reg", 0x03, 0x1030 }, // set GRAM write direction.

145 // { "reg", 0x03, 0x1020 }, // set GRAM write direction.

146 #endif

147 { "reg", 0x07, 0x0000 }, // Display off

148 { "reg", 0x08, 0x0808 },

149 { "reg", 0x0B, 0x1100 },

150 { "reg", 0x0C, 0x0000 },

151 { "reg", 0x0F, 0x0501 }, // Set Osc

152 { "reg", 0x15, 0x0020 }, // Set VCI recycling

153 { "reg", 0x20, 0x0000 }, // RAM Address

154 { "reg", 0x21, 0x0000 }, // RAM Address

155

156 //------------------------ Set GRAM area --------------------------------//

157 { "reg", 0x30, 0x0000 },

158 { "reg", 0x31, 0x00DB },

159 { "reg", 0x32, 0x0000 },

160 { "reg", 0x33, 0x0000 },

161 { "reg", 0x34, 0x00DB },

162 { "reg", 0x35, 0x0000 },

163 { "reg", 0x36, 0x00AF },

164 { "reg", 0x37, 0x0000 },

165 { "reg", 0x38, 0x00DB },

166 { "reg", 0x39, 0x0000 },

167

168

169 // ---------- Adjust the Gamma 2.2 Curve -------------------//

170 { "reg", 0x50, 0x0603},

171 { "reg", 0x51, 0x080D},

172 { "reg", 0x52, 0x0D0C},

173 { "reg", 0x53, 0x0205},

174 { "reg", 0x54, 0x040A},

175 { "reg", 0x55, 0x0703},

176 { "reg", 0x56, 0x0300},

177 { "reg", 0x57, 0x0400},

178 { "reg", 0x58, 0x0B00},

179 { "reg", 0x59, 0x0017},

180

181 { "reg", 0x0F, 0x0701}, // Vertical RAM Address Position

182 { "reg", 0x07, 0x0012}, // Vertical RAM Address Position

183 { "msleep", 50, 0}, //mdelay( 50 }, // Delay 50 ms

184 { "reg", 0x07, 0x1017}, // Vertical RAM Address Position

185

186 };

187

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197

198

199

200

201 /*-------------------------GPIO base ----------------------------------------------------------------------*/

202

203

204 #define GPIO_OUT_H 1

#define GPIO_OUT_L 0

206

207 static int base_gpio_set(int gpio,int value)

208 {

209 unsigned int tmp;

210 if (gpio <= 31) {

211 tmp = le32_to_cpu(*(volatile u32 *)(RALINK_REG_PIODIR));

212 tmp |= 1 << gpio;

213 *(volatile u32 *)(RALINK_REG_PIODIR) = tmp;

214

215 tmp = le32_to_cpu(*(volatile u32 *)(RALINK_REG_PIODATA));

216 tmp &= ~(1 << gpio);

217 tmp |= value << gpio;

218 *(volatile u32 *)(RALINK_REG_PIODATA) = cpu_to_le32(tmp);

219 // *(volatile u32 *)(RALINK_REG_PIOSET) = cpu_to_le32(tmp);

220 } else if (gpio <= 63) {

221 tmp = le32_to_cpu(*(volatile u32 *)(RALINK_REG_PIODIR + 0x04));

222 tmp |= 1 << (gpio - 32);

223 *(volatile u32 *)(RALINK_REG_PIODIR + 0x04) = tmp;</