soc 设计soc设计 uml实务手册_无线相关职位：PHY设计/验证 MAC设计/验证 SOC验证

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无线连接PHY设计工程师

Job overview:

The digital design engineer will be responsible for designing our wireless PHY IP. This position requires working closely with our architecture algorithm and design engineers to explore ideas for next generation products and develop RTL to turn these ideas into customized solutions.

Duties/Responsibilities:

1. Based on IP feature specification finish RTL design

2. Work with verification, synthesis and timing team to finish qualified delivery

3. Support FPGA emulation, lab validation and debugging。

工作要求

Qualifications:

1. BS in Electrical/ Electronic Engineering, MS preferred

2. 3 years working experience with Verilog, System Verilog programming, logic synthesis and gate level timing closure. A record of delivering successful ASICs to market is preferred

3. Strong background in digital communication signal processing.

4. Experience on deliver following modules: AGC, FFT, channel estimation, beamforming, LDPC, carrier track, symbol timing track is highly preferred.

5. Experience on 802.11, Bluetooth, GNSS and UWB is highly preferred.

Skill and Experience:

1. Must be proficient in RTL coding, logic synthesis, gate level timing

2. Experience in the area of automatic code generation is a plus, Perl, Python and Unix Shell experience is a plus

3. Experience on communication ASICs is a plus

4. Good knowledge of IC design backend flow. Experience in IC life-cycle from conception, design, verification, top level delivery with pads to tape-out, chip-testing and mass production。

无线连接PHY验证工程师

工作职责

Job overview: The digital phy verification engineer will be responsible for the simulation and verification of wireless SOC ASICs. This position requires working with our design engineers and algorithm engineers to prove correctness and measure performance of our algorithm and RTL design. Responsibility include developing simulation environment used by our test development team to exercise C/SystemC/MATLAB/Verilog models, as well as evaluate third party tool and develop methodologies which enhance ability to produce high quality ASICs. 

Duties/Responsibilities: 

1. Developing simulation environment, and evaluate third party tools and develop methodologies 

2. Design direct or random simulation test cases/sequences

 3. Support FPGA emulation, lab validation and debugging.

工作要求Qualifications: 

1. BS in Electrical/ Electronic Engineering, MS preferred 

2. 1-3 years working experience with various verification flow is required with the proven track record of delivery successful ASICs 

3. Strong background in software is a must, along with familiarity with ASICS design flow

 4. One and more advantage as following are highly desirable: IC DV experience in wireless communication like Wifi/Bluetooth/UWB; a strong background in digital communication signal processing; 

5. Good communication skill in English 

Skill and Experience: 

1. Strong background and experience required in UVM, SystemC/C++/C, Matlab, Verilog, System Verilog and ASIC verification technique 

2. Experience in the area of automatic code generation is a plus, Python/Perl/Makefile and Unix Shell experience is a plus 

3. Experience on communication ASICs is a plus 

4. Good knowledge of IC design backend flow 5. FPGA PCB or embedded software skill is a plus。

无线链接SOC验证工程师

工作职责Job overview: The connectivity SOC verification engineer will be responsible for the simulation and verification of wireless SOC chips. This position requires working with our architecture algorithm and design engineers to prove correctness and measure performance of our algorithm and RTL design. Responsibility include developing simulation environment used by our test development team to exercise MATLAB and Verilog model, as well as evaluate third party tool and develop methodologies which enhance ability to produce high quality chips.

 Duties/Responsibilities: 

1. Developing reusable testbench, and evaluate third party tools and develop advanced methodologies 

2. Obtain the highest verification quality of SOC with high efficiency; 

3. Design direct or random simulation test cases to exercise Matlab and Verilog models 

4. Support FPGA emulation, lab validation and debugging 

5. Help to CHIP bring up

工作要求Qualifications: 

1. BS in Electrical/ Electronic Engineering, MS preferred 

2. 1-3 years working experience with various verification flow is required with the proven track record of delivery successful SOCs 

3. Strong background in software is a must, along with familiarity with SOC design flow 

4. One and more advantage as following are highly desirable: a strong background in digital communication signal processing and network protocol; IC DV experience in wireless communication and audio processing; 

5. Experience with ARM/DSP AMBA bus and External interface development like PCIE, USB etc. 

6. Good communication skill in English 

Skill and Experience:

 1. Strong background and experience required in C/C++ Verilog, System Verilog and SOC verification technique 

2. Having advanced knowledge of HVL methodology (UVM/OVM/VMM) 

3. Must be proficient in problem solving, constrained random testing, and debugging 

4. Having low power verification experience 

5. Experience defining coverage space and writing coverage model a plus 

6. Familiar with SOC verification flow, and experience Palladium/ZEBU simulation accelerator is plus

 7. Experience in the area of automatic code generation is a plus, Perl, Python and Unix Shell experience is a plus 

8. Experience on high speed interface (PCIE, USB, Ethernet) is a plus 

9. Good knowledge of the whole IC development flow

无线链接MAC设计工程师

Job overview: The digital design engineer will be responsible for designing our MAC IP. This position requires working closely with our architecture algorithm and discuss hardware and software interface with software team.design engineers to explore ideas for next generation products and develop RTL to turn these ideas into customized solutions. 

Duties/Responsibilities: 

1. Based on wifi and bluetooth specification finish RTL design 

2. Based on chip feature specification finish RTL design

 3. Work with verification, synthesis and timing team to finish qualified delivery 

4. Support FPGA emulation, lab validation and debugging.

工作要求Qualifications: 

1. BS in Electrical/ Electronic Engineering, MS preferred 

2. 3 years working experience with Verilog, System Verilog programming, logic synthesis and gate level timing closure. A record of delivering successful ASICs to market is preferred 

3. design experience in wireless communication and familiar with wifi or bt protocol; 

4. experience in ring control and fetch descriptor for dma; 

5. strong background in digital communication signal processing and network protocol; 

6. Experience with ARM/DSP AMBA bus and External interface development like PCIE etc 

Skill and Experience: 

1. Must be proficient in RTL coding, logic synthesis, gate level timing 

2. Experience in the area of automatic code generation is a plus, Perl, Python and Unix Shell experience is a plus 

3. Experience on communication ASICs is a plus 

4. Good knowledge of IC design backend flow

 5. Experience in IC life-cycle from conception, design, verification, top level delivery with pads to tape-out, chip-testing and mass production 6. FPGA PCB or embedded software skill is a plus.

无线连接MAC验证工程师

工作职责Job overview: The digital verification engineer will be responsible for the simulation and verification of wireless SOC ASICs. This position requires working with our design engineers and architecture engineers to prove correctness and measure performance of our algorithm and RTL design. Responsibility include developing simulation environment used by our test development team to exercise SystemVerilog/C/Verilog/MATLAB models, as well as evaluate third party tool and develop methodologies which enhance ability to produce high quality ASICs. 

Duties/Responsibilities: 

1. Developing simulation environment, and evaluate third party tools and develop methodologies 

2. Design direct or random simulation test cases/sequences 

3. Support FPGA emulation, lab validation and debugging。

工作要求Qualifications: 

1. BS in Electrical/ Electronic Engineering, MS preferred 

2. 1-3 years working experience with various verification flow is required with the proven track record of delivery successful ASICs 

3. Strong background in software is a must, along with familiarity with ASICS design flow 

4. One and more advantage as following are highly desirable: IC DV experience in wireless communication like Wifi/Bluetooth/UWB; a strong background in network protocol or digital communication signal processing; Experience with ARM/DSP AMBA bus and External interface development like PCIE etc. 

5. Good communication skill in English 

Skill and Experience: 

1. Strong background and experience required in UVM, C/C++ Verilog, System Verilog and ASIC verification technique 

2. Experience in the area of automatic code generation is a plus, Python/Perl/Makefile and Unix Shell experience is a plus

 3. Experience on communication ASICs is a plus 4. Good knowledge of IC design backend flow 5. FPGA PCB or embedded software skill is a plus。