项目场景：
lk中配置spi,不受控，写寄存器时卡死
测试程序：
void spi_test11()
{
unsigned char *tx_buf1;
unsigned int data_size = 32;
struct qup_spi_dev *spi_dev;
dprintf(CRITICAL, "-----start %s----\n", __func__);
tx_buf1 = malloc(data_size);
spi_dev = qup_blsp_spi_init(BLSP_ID_2, QUP_ID_1);
dprintf(CRITICAL, "-----%s--%d--\n", __func__,__LINE__);
if (!spi_dev) {
dprintf(CRITICAL, "Failed initializing SPI\n");
return;
}
dprintf(CRITICAL, "-1----%s--%d--\n", __func__,__LINE__);
spidev_write_cmd(spi_dev, ((0x3c<<1)|0x01));
dprintf(CRITICAL, "--2---%s--%d--\n", __func__,__LINE__);
free(tx_buf1);
dprintf(CRITICAL, "--end---%s--%d--\n", __func__,__LINE__);
}
问题描述
1.spi7 卡死(gpio85-88)
2.spi6 正常（gpio20-23）
原因分析：
bootable/bootloader/lk/platform/msm8952/acpuclock.c
--- a/bootable/bootloader/lk/platform/msm8952/acpuclock.c
+++ b/bootable/bootloader/lk/platform/msm8952/acpuclock.c
@@ -515,14 +515,21 @@ void clock_config_blsp_spi(uint8_t blsp_id, uint8_t qup_id, unsigned long rate)
uint8_t ret = 0;
char clk_name[64];
- qup_id = qup_id + 1;
+ //qup_id = qup_id + 1;
- if ((blsp_id != BLSP_ID_1)) {
+ /* if ((blsp_id != BLSP_ID_1) || (blsp_id != BLSP_ID_2)) {
dprintf(CRITICAL, "Incorrect BLSP-%d configuration\n", blsp_id);
ASSERT(0);
- }
+ } */
- snprintf(clk_name, sizeof(clk_name), "blsp1_ahb_iface_clk");
+/* snprintf(clk_name, sizeof(clk_name), "blsp1_ahb_iface_clk"); */
+
+ if((blsp_id == BLSP_ID_1))
+ snprintf(clk_name, sizeof(clk_name), "blsp1_ahb_iface_clk");
+ else if((blsp_id == BLSP_ID_2))
+ snprintf(clk_name, sizeof(clk_name), "blsp2_ahb_iface_clk");
+
+ dprintf(CRITICAL, "-----0 %s----\n", __func__);
ret = clk_get_set_enable(clk_name, 0, 1);
@@ -531,12 +538,18 @@ void clock_config_blsp_spi(uint8_t blsp_id, uint8_t qup_id, unsigned long rate)
__func__, clk_name);
return;
}
+ dprintf(CRITICAL, "-----1 %s----\n", __func__);
- snprintf(clk_name, sizeof(clk_name), "gcc_blsp1_qup%u_spi_apps_clk",
- qup_id);
+ //snprintf(clk_name, sizeof(clk_name), "gcc_blsp1_qup%u_spi_apps_clk",
+ //qup_id);
+ if ((blsp_id == BLSP_ID_1))
+ snprintf(clk_name, sizeof(clk_name), "gcc_blsp1_qup%u_spi_apps_clk",qup_id);
+ else if ((blsp_id == BLSP_ID_2))
+ snprintf(clk_name, sizeof(clk_name), "gcc_blsp2_qup2_spi_apps_clk");
/* Set the highest clk frequency by default for good performance. */
ret = clk_get_set_enable(clk_name, rate, 1);
+ dprintf(CRITICAL, "-----2 %s----\n", __func__);
if (ret) {
dprintf(CRITICAL, "%s: Failed to enable %s\n",
bootable/bootloader/lk/platform/msm8952/include/platform/iomap.h
--- a/bootable/bootloader/lk/platform/msm8952/include/platform/iomap.h
+++ b/bootable/bootloader/lk/platform/msm8952/include/platform/iomap.h
@@ -71,7 +71,8 @@
#define MSM_USB_BASE (PERIPH_SS_BASE + 0x000DB000)
#define CLK_CTL_BASE 0x1800000
-#define BLSP_QUP_BASE(blsp_id, qup_id) (PERIPH_SS_BASE + 0xB5000 + 0x1000 * qup_id)
+//#define BLSP_QUP_BASE(blsp_id, qup_id) (PERIPH_SS_BASE + 0xB5000 + 0x1000 * qup_id)
+#define BLSP_QUP_BASE(blsp_id, qup_id) ((blsp_id == 1)?(PERIPH_SS_BASE + 0xB5000 + 0x1000 * qup_id):0x7af6000)
//spi7 -0x7af7000
#define PMI_SLAVE_BASE 2
#define PMI_FIRST_SLAVE_OFFSET 0
#define PMI_SECOND_SLAVE_OFFSET 1
@@ -172,6 +173,22 @@
#define GCC_BLSP1_QUP5_SPI_APPS_N (CLK_CTL_BASE + 0x6030)
#define GCC_BLSP1_QUP5_SPI_APPS_D (CLK_CTL_BASE + 0x6034)
+#define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x0B008)
+
+#define GCC_BLSP2_QUP2_SPI_APPS_CBCR (CLK_CTL_BASE + 0xD00C)
+#define GCC_BLSP2_QUP2_SPI_APPS_CMD_RCGR (CLK_CTL_BASE + 0xD014)
+#define GCC_BLSP2_QUP2_SPI_CFG_RCGR (CLK_CTL_BASE + 0xD018)
+#define GCC_BLSP2_QUP2_SPI_APPS_M (CLK_CTL_BASE + 0xD01C)
+#define GCC_BLSP2_QUP2_SPI_APPS_N (CLK_CTL_BASE + 0xD020)
+#define GCC_BLSP2_QUP2_SPI_APPS_D (CLK_CTL_BASE + 0xD024)
+
+#define GCC_BLSP2_QUP3_SPI_APPS_CBCR (CLK_CTL_BASE + 0xf01C)
+#define GCC_BLSP2_QUP3_SPI_APPS_CMD_RCGR (CLK_CTL_BASE + 0xf024)
+#define GCC_BLSP2_QUP3_SPI_CFG_RCGR (CLK_CTL_BASE + 0xf028)
+#define GCC_BLSP2_QUP3_SPI_APPS_M (CLK_CTL_BASE + 0xf02C)
+#define GCC_BLSP2_QUP3_SPI_APPS_N (CLK_CTL_BASE + 0xf030)
+#define GCC_BLSP2_QUP3_SPI_APPS_D (CLK_CTL_BASE + 0xf034)
+
/* USB */
#define USB_HS_BCR (CLK_CTL_BASE + 0x41000)
bootable/bootloader/lk/platform/msm8952/include/platform/irqs.h
--- a/bootable/bootloader/lk/platform/msm8952/include/platform/irqs.h
+++ b/bootable/bootloader/lk/platform/msm8952/include/platform/irqs.h
@@ -48,7 +48,8 @@
#define USB1_HS_IRQ (GIC_SPI_START + 134)
#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 138)
#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
-#define BLSP_QUP_IRQ(blsp_id, qup_id) (GIC_SPI_START + 95 + qup_id)
+//#define BLSP_QUP_IRQ(blsp_id, qup_id) (GIC_SPI_START + 95 + qup_id)
+#define BLSP_QUP_IRQ(blsp_id, qup_id) ((blsp_id == 1)?((GIC_SPI_START + 95) + qup_id):((GIC_SPI_START + 299) + qup_id))
/* Retrofit universal macro names */
#define INT_USB_HS USB1_HS_IRQ
bootable/bootloader/lk/platform/msm8952/msm8952-clock.c
--- a/bootable/bootloader/lk/platform/msm8952/msm8952-clock.c
+++ b/bootable/bootloader/lk/platform/msm8952/msm8952-clock.c
@@ -342,6 +342,18 @@ static struct vote_clk gcc_blsp1_ahb_clk = {
},
};
+static struct vote_clk gcc_blsp2_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(20),
+
+ .c = {
+ .dbg_name = "gcc_blsp2_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+
static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk[] = {
F( 960000, cxo, 10, 1, 2),
F( 4800000, cxo, 4, 0, 0),
@@ -353,6 +365,7 @@ static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk[] = {
F_END
};
+
static struct rcg_clk gcc_blsp1_qup3_spi_apps_clk_src = {
.cmd_reg = (uint32_t *) GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR,
.cfg_reg = (uint32_t *) GCC_BLSP1_QUP3_SPI_CFG_RCGR,
@@ -430,6 +443,62 @@ static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = {
};
+static struct rcg_clk gcc_blsp2_qup2_spi_apps_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_BLSP2_QUP2_SPI_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_BLSP2_QUP2_SPI_CFG_RCGR,
+ .m_reg = (uint32_t *) GCC_BLSP2_QUP2_SPI_APPS_M,
+ .n_reg = (uint32_t *) GCC_BLSP2_QUP2_SPI_APPS_N,
+ .d_reg = (uint32_t *) GCC_BLSP2_QUP2_SPI_APPS_D,
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "gcc_blsp2_qup2_spi_apps_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_blsp2_qup2_spi_apps_clk = {
+ .cbcr_reg = (uint32_t *) GCC_BLSP2_QUP2_SPI_APPS_CBCR,
+ .parent = &gcc_blsp2_qup2_spi_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp2_qup2_spi_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+
+
+
+static struct rcg_clk gcc_blsp2_qup3_spi_apps_clk_src = {
+ .cmd_reg = (uint32_t *) GCC_BLSP2_QUP3_SPI_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) GCC_BLSP2_QUP3_SPI_CFG_RCGR,
+ .m_reg = (uint32_t *) GCC_BLSP2_QUP3_SPI_APPS_M,
+ .n_reg = (uint32_t *) GCC_BLSP2_QUP3_SPI_APPS_N,
+ .d_reg = (uint32_t *) GCC_BLSP2_QUP3_SPI_APPS_D,
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "gcc_blsp2_qup3_spi_apps_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_blsp2_qup3_spi_apps_clk = {
+ .cbcr_reg = (uint32_t *) GCC_BLSP2_QUP3_SPI_APPS_CBCR,
+ .parent = &gcc_blsp2_qup3_spi_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp2_qup3_spi_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+
/* USB Clocks */
static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
{
@@ -703,6 +772,12 @@ static struct clk_lookup msm_clocks_8952[] =
CLK_LOOKUP("gcc_blsp1_qup4_spi_apps_clk", gcc_blsp1_qup4_spi_apps_clk.c),
CLK_LOOKUP("gcc_blsp1_qup5_spi_apps_clk_src", gcc_blsp1_qup5_spi_apps_clk_src.c),
CLK_LOOKUP("gcc_blsp1_qup5_spi_apps_clk", gcc_blsp1_qup5_spi_apps_clk.c),
+
+ CLK_LOOKUP("blsp2_ahb_iface_clk", gcc_blsp2_ahb_clk.c),
+ CLK_LOOKUP("gcc_blsp2_qup2_spi_apps_clk_src", gcc_blsp2_qup2_spi_apps_clk_src.c),
+ CLK_LOOKUP("gcc_blsp2_qup2_spi_apps_clk", gcc_blsp2_qup2_spi_apps_clk.c),
+ CLK_LOOKUP("gcc_blsp2_qup3_spi_apps_clk_src", gcc_blsp2_qup3_spi_apps_clk_src.c),
+ CLK_LOOKUP("gcc_blsp2_qup3_spi_apps_clk", gcc_blsp2_qup3_spi_apps_clk.c),
CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c),
CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c),
bootable/bootloader/lk/platform/msm8952/gpio.c
--- a/bootable/bootloader/lk/platform/msm8952/gpio.c
+++ b/bootable/bootloader/lk/platform/msm8952/gpio.c
@@ -140,6 +140,47 @@ void gpio_config_blsp_spi(uint8_t blsp_id, uint8_t qup_id)
dprintf(CRITICAL, "Incorrect QUP id %d\n", qup_id);
ASSERT(0);
};
+ }
+ else if (blsp_id == BLSP_ID_2) {
+ switch (qup_id) {
+ case QUP_ID_1:
+ /* configure SPI MOSI gpio */
+ gpio_tlmm_config(20, 1, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_16MA, GPIO_DISABLE);
+
+ /* configure SPI MISO gpio */
+ gpio_tlmm_config(21, 1, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_16MA, GPIO_DISABLE);
+
+ /* configure SPI CS_N gpio */
+ gpio_tlmm_config(22, 1, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_16MA, GPIO_DISABLE);
+
+ /* configure SPI CLK gpio */
+ gpio_tlmm_config(23, 1, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_16MA, GPIO_DISABLE);
+ break;
+ case QUP_ID_2:
+ /* configure SPI MOSI gpio */
+ gpio_tlmm_config(85, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_16MA, GPIO_DISABLE);
+
+ /* configure SPI MISO gpio */
+ gpio_tlmm_config(86, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_16MA, GPIO_DISABLE);
+
+ /* configure SPI CS_N gpio */
+ gpio_tlmm_config(87, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_16MA, GPIO_DISABLE);
+
+ /* configure SPI CLK gpio */
+ gpio_tlmm_config(88, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_16MA, GPIO_DISABLE);
+ break;
+ default:
+ dprintf(CRITICAL, "Incorrect QUP id %d\n", qup_id);
+ ASSERT(0);
+ };
} else {
dprintf(CRITICAL, "Incorrect BLSP id %d\n", blsp_id);
ASSERT(0);
解决方案：
对比pinctrl-msm8917.c源码，最后是function 配置错误导致，原先配置成1了，应该要配置成2：
411
被折叠的 条评论
为什么被折叠?
到【灌水乐园】发言
