DAC9881

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/11/21 15:30:01
// Design Name: 
// Module Name: DAC9881
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module DAC9881(
    input clk,
    input rstb,
    input [31:0] ival,
    output o_cs,
    output o_sck,
    output o_sda
    );
    
logic s_cs;
logic s_sck;
logic s_sda;

assign o_cs = s_cs;
assign o_sck = s_sck;
assign o_sda = s_sda;
  
logic [1:0]step;
logic [5:0] cnt;
logic odd;
logic [22:0] ival_shift;    
  always @(posedge clk or negedge rstb)begin
       if(!rstb)begin 
            step <= 0;
            s_cs <= 1;
            s_sck <= 0;
            s_sda <= 0;
            cnt<=0;
       end else if(step==0)begin        //init
            s_cs <= 0;
            cnt <= 24;
            step<=1;
            s_sck <= 0;
            odd <= 1;
            ival_shift <= ival[22:0];
            s_sda<=ival[23];
       end else if(step==1) begin 
            if(cnt != 0)begin
                if(odd==1'b0)begin
                    s_sda <= ival_shift[22];
                    ival_shift <= {ival_shift[21:0],1'b0};
                    s_sck <= 0;
                end else begin
                    s_sda <= s_sda;
                    s_sck <= 1;
                    cnt <= cnt - 1;
                end     
            end else begin      
                cnt <= 0;
                step <= 2;
                s_sck <= 0;
            end
            odd <= ~odd;
       end else if(step==2)begin
            step <= 0;
            s_cs<=1;
       end
    end    
    
    
endmodule

 CLK Input :100M

 Latency    : 50

DAC Modulated frequency : 2M