ADC LTC2325 lvds

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/11/15 11:16:24
// Design Name: 
// Module Name: LTC2325
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module LTC2325_lvds(
    input clk,
    input rstb,
    input clk_200,
    input clk_220,
    output  o_ADC_CNV       ,
    output  o_ADC_SDR       ,
    output  o_ADC_LVDS      ,
    input   i_ADC_DA_p      ,
    input   i_ADC_DA_n      ,
    input   i_ADC_DB_p      ,
    input   i_ADC_DB_n      ,
    input   i_ADC_DC_p      ,
    input   i_ADC_DC_n      ,
    input   i_ADC_DD_p      ,
    input   i_ADC_DD_n      ,
    output  o_ADC_CLK_IN_p  ,
    output  o_ADC_CLK_IN_n  ,
    input   i_ADC_CLK_OUT_p ,
    input   i_ADC_CLK_OUT_n ,
    output [11:0]dout0,
    output [11:0]dout1,
    output [11:0]dout2,
    output [11:0]dout3,
    output dvalid
    );
    
//DDR & lvds mode
assign o_ADC_SDR = 1;   
assign o_ADC_LVDS = 1;

logic SCKn;
logic CLKOUTn;
logic SDO_An;
logic SDO_Bn;
logic SDO_Cn;
logic SDO_Dn;
logic SDO_An_dly;
logic SDO_Bn_dly;
logic SDO_Cn_dly;
logic SDO_Dn_dly;

logic SDO_An_sample;
logic SDO_Bn_sample;
logic SDO_Cn_sample;
logic SDO_Dn_sample;
assign SDO_An_sample = SDO_An_dly;
assign SDO_Bn_sample = SDO_Bn_dly;
assign SDO_Cn_sample = SDO_Cn_dly;
assign SDO_Dn_sample = SDO_Dn_dly;

ila_1 ila_test2 (
	.clk(clk_220), // input wire adc0_delay_inst
	
	.probe0(dout0), // input wire [31:0]  probe0  
	.probe1(dout1), // input wire [31:0]  probe1 
	.probe2(dout2), // input wire [31:0]  probe2 
	.probe3(dout3), // input wire [31:0]  probe3 
	.probe4(dvalid), // input wire [0:0]  probe4 
	.probe5(SCKn), // input wire [0:0]  probe5 
	.probe6(CLKOUTn), // input wire [0:0]  probe6 
	.probe7(o_ADC_CNV), // input wire [0:0]  probe7 
	.probe8(SDO_An_sample), // input wire [0:0]  probe8 
	.probe9(SDO_Bn_sample), // input wire [0:0]  probe9 
	.probe10(SDO_Cn_sample), // input wire [0:0]  probe10 
	.probe11(SDO_Dn_sample) // input wire [0:0]  probe11
);
//tarnsfer-shift data stage
logic [15:0] DA_SHIFT;
logic [15:0] DB_SHIFT;
logic [15:0] DC_SHIFT;
logic [15:0] DD_SHIFT;
//store-sample value
logic [12:0] SDOA_data;
logic [12:0] SDOB_data;
logic [12:0] SDOC_data;
logic [12:0] SDOD_data;
logic SDO_valid;
assign dout0 = SDOA_data;
assign dout1 = SDOB_data;
assign dout2 = SDOC_data;
assign dout3 = SDOD_data;
assign dvalid = SDO_valid;

//generate step signal (110M)
logic [4:0] step;   
always @(posedge clk or negedge rstb)begin
    if(~rstb)begin
        step <= 0;
    end else begin
        if(step>=21)
            step <= 0;
        else
            step <= step + 1;
    end
end

//convert statge
logic r_CNV;
assign o_ADC_CNV = r_CNV;
always @(posedge clk or negedge rstb)begin
    if(~rstb)begin
        r_CNV <= 0;
    end else begin
        if(step>=4)
            r_CNV<=0;
        else
            r_CNV<=1;
    end
end
//transfer state
logic o_SCK;
assign SCKn = o_SCK;
always @(posedge clk or negedge rstb)begin
    if(~rstb)begin
        o_SCK <= 0;
        DA_SHIFT <= 0;
        DB_SHIFT <= 0;
        DC_SHIFT <= 0;
        DD_SHIFT <= 0;
    end else begin
        if(step>=6)begin
            if(step[0]==1'b1)begin
                o_SCK<=0;
                DA_SHIFT <= {DA_SHIFT[14:0],SDO_An_sample};
                DB_SHIFT <= {DB_SHIFT[14:0],SDO_Bn_sample};
                DC_SHIFT <= {DC_SHIFT[14:0],SDO_Cn_sample};
                DD_SHIFT <= {DD_SHIFT[14:0],SDO_Dn_sample};
            end else begin
                o_SCK<=1;
                DA_SHIFT <= {DA_SHIFT[14:0],SDO_An_sample};
                DB_SHIFT <= {DB_SHIFT[14:0],SDO_Bn_sample};
                DC_SHIFT <= {DC_SHIFT[14:0],SDO_Cn_sample};
                DD_SHIFT <= {DD_SHIFT[14:0],SDO_Dn_sample};
             end
        end else begin 
            o_SCK<=0;
        end 
    end
end







always @(posedge clk or negedge rstb)begin
    if(~rstb)begin
        SDOA_data <= 0;
        SDOB_data <= 0;
        SDOC_data <= 0;
        SDOD_data <= 0;
        SDO_valid <= 0;
    end else begin
        if(step==0)begin
        
            if(DA_SHIFT[15]==1'b1)
                SDOA_data <= 4095;
            else
                SDOA_data <= {DA_SHIFT[14:3]};
                
            if(DB_SHIFT[15]==1'b1)
                SDOB_data <= 4095;
            else
                SDOB_data <= {DB_SHIFT[14:3]};
            if(DC_SHIFT[15]==1'b1)
                SDOC_data<=4095;
            else
                SDOC_data <= {DC_SHIFT[14:3]};
            if(DD_SHIFT[15]==1'b1)
                SDOD_data<=4095;
            else
                SDOD_data <= {DD_SHIFT[14:3]};
                
            SDO_valid <= 1;
        end else begin
            SDOA_data <= SDOA_data;
            SDOB_data <= SDOB_data;
            SDOC_data <= SDOC_data;
            SDOD_data <= SDOD_data;
            SDO_valid <= 0;
        end
    end
end



//signal delay & diff to sigle mode

OBUFDS U_SCKn(.I(SCKn),            
              .O(o_ADC_CLK_IN_p),  
              .OB(o_ADC_CLK_IN_n));
IBUFGDS U_CLKOUTn(.I(i_ADC_CLK_OUT_p),
             .IB(i_ADC_CLK_OUT_n),
             .O(CLKOUTn));     
IBUFDS U_SDO_An (.I(i_ADC_DA_p),
               .IB(i_ADC_DA_n),
               .O(SDO_An));
IBUFDS U_SDO_Bn (.I(i_ADC_DB_p),
               .IB(i_ADC_DB_n),
               .O(SDO_Bn));
IBUFDS U_SDO_Cn (.I(i_ADC_DC_p),
               .IB(i_ADC_DC_n),
               .O(SDO_Cn));
IBUFDS U_SDO_Dn (.I(i_ADC_DD_p),
               .IB(i_ADC_DD_n),
               .O(SDO_Dn));
               
(* IODELAY_GROUP = "ADC_DLY_CONTROL1" *)    // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYCTRL IDELAYCTRL_inst (
    .RDY(RDY),
    .REFCLK(clk_200),               // 1-bit input: Reference clock input
    .RST(!rstb)                   // 1-bit input: Active high reset input
);
`define     ADC_DELAY   0
(* IODELAY_GROUP = "ADC_DLY_CONTROL1" *)
IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("FALSE"),
    .IDELAY_TYPE("FIXED"),
    .IDELAY_VALUE(`ADC_DELAY),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.0),
    .SIGNAL_PATTERN("DATA")
)
adc0_delay_inst (
    .DATAOUT(SDO_An_dly),
    .C(clk_200),
    .CE(1'b0),
    .CINVCTRL(1'b0),
    .CNTVALUEIN(0),
    .DATAIN(1'b0),
    .IDATAIN(SDO_An),
    .INC(1'b0),
    .LD(1'b0),
    .LDPIPEEN(1'b0),
    .REGRST(!rstb)
);
(* IODELAY_GROUP = "ADC_DLY_CONTROL1" *)
IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("FALSE"),
    .IDELAY_TYPE("FIXED"),
    .IDELAY_VALUE(`ADC_DELAY),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.0),
    .SIGNAL_PATTERN("DATA")
)
adc1_delay_inst (
    .DATAOUT(SDO_Bn_dly),
    .C(clk_200),
    .CE(1'b0),
    .CINVCTRL(1'b0),
    .CNTVALUEIN(0),
    .DATAIN(1'b0),
    .IDATAIN(SDO_Bn),
    .INC(1'b0),
    .LD(1'b0),
    .LDPIPEEN(1'b0),
    .REGRST(!rstb)
);
(* IODELAY_GROUP = "ADC_DLY_CONTROL1" *)
IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("FALSE"),
    .IDELAY_TYPE("FIXED"),
    .IDELAY_VALUE(`ADC_DELAY),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.0),
    .SIGNAL_PATTERN("DATA")
)
adc2_delay_inst (
    .DATAOUT(SDO_Cn_dly),
    .C(clk_200),
    .CE(1'b0),
    .CINVCTRL(1'b0),
    .CNTVALUEIN(0),
    .DATAIN(1'b0),
    .IDATAIN(SDO_Cn),
    .INC(1'b0),
    .LD(1'b0),
    .LDPIPEEN(1'b0),
    .REGRST(!rstb)
);
(* IODELAY_GROUP = "ADC_DLY_CONTROL1" *)
IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("FALSE"),
    .IDELAY_TYPE("FIXED"),
    .IDELAY_VALUE(`ADC_DELAY),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.0),
    .SIGNAL_PATTERN("DATA")
)
adc3_delay_inst (
    .DATAOUT(SDO_Dn_dly),
    .C(clk_200),
    .CE(1'b0),
    .CINVCTRL(1'b0),
    .CNTVALUEIN(0),
    .DATAIN(1'b0),
    .IDATAIN(SDO_Dn),
    .INC(1'b0),
    .LD(1'b0),
    .LDPIPEEN(1'b0),
    .REGRST(!rstb)
);


endmodule

CLK input : 110M