uboot启动流程概述_powerpc uboot启动流程分析

在arch/powerpc/cpu/mpc85xx 下有两个.S文件

release.S

start.S

在release.S中代码只有两行.section .resetvec,"ax"

b _start_e500

跳转到start.S中执行

.section .bootpg,"ax"

.globl _start_e500

_start_e500:

/* clear registers/arrays not reset by hardware */

/* L1 */

li    r0,2

mtspr    L1CSR0,r0    /* invalidate d-cache */

mtspr    L1CSR1,r0    /* invalidate i-cache */

mfspr    r1,DBSR

mtspr    DBSR,r1        /* Clear all valid bits */

/*

*    Enable L1 Caches early

*

*/

。。。。。。

435         bl      cpu_init_early_f

436

437         /* switch back to AS = 0 */

438         lis     r3,(MSR_CE|MSR_ME|MSR_DE)@h

439         ori     r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l

440         mtmsr   r3

441         isync

442

443         bl      cpu_init_f

444         bl      board_init_f

445         isync

446

＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊

#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")

[/code]

大概的意思是声明一个指向gd_t结构体变量的指针gd，并固定使用寄存器r8来存放该指针。而对gd_t结构体的定义从上面的第36行开始：

cpu_init_early_f在arch/powerpc/cpu/mpc85xx/ cpu_init_early.c

/* We run cpu_init_early_f in AS = 1 */

73 void cpu_init_early_f(void)//设置tlb

/* We run cpu_init_early_f in AS = 1 */

73 void cpu_init_early_f(void)

74 {

75         u32 mas0, mas1, mas2, mas3, mas7;

76         int i;

77

78         /* Pointer is writable since we allocated a register for it */

79         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);

80

81         /*

82          * Clear initial global data

83          *   we don't use memset so we can share this code with NAND_SPL

84          */

85         for (i = 0; i < sizeof(gd_t); i++)

86                 ((char *)gd)[i] = 0;

87

88         mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0);

89         mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);

90         mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);

91         mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);

92         mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);

93

94         write_tlb(mas0, mas1, mas2, mas3, mas7);

95

96         /* set up CCSR if we want it moved */

97 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)

98         mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);

99         /* mas1 is the same as above */

100         mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G);

101         mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, MAS3_SW|MAS3_SR);

102         mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT);

103

104         write_tlb(mas0, mas1, mas2, mas3, mas7);

105

106         setup_ccsrbar();

107 #endif

108

109         init_laws();

110         invalidate_tlb(0);

111         init_tlbs();

112 }

*******************************

cpu_init_f() 在cpu_init.c中

203 void cpu_init_f (void)

204 {

205         extern void m8560_cpm_reset (void);

206 #ifdef CONFIG_MPC8548

207         ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);

208         uint svr = get_svr();

209

210         /*

211          * CPU2 errata workaround: A core hang possible while executing

212          * a msync instruction and a snoopable transaction from an I/O

213          * master tagged to make quick forward progress is present.

214          * Fixed in silicon rev 2.1.

215          */

216         if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))

217                 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));

218 #endi