[reference]-ARM/TEE/security等论文中的缩写和参考文献

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缩写对比表

Platform Security Boot Guide.pdf

AES 			Advanced Encryption Standard, a symmetric-key encryption standard
Digest 			The output of a hash operation
DoS 			Denial of Service
EEPROM 			Electrically Erasable Programmable Read-Only Memory
eFlash 			See Internal flash
eFuse 			OTP memory, available in very limited quantity
HMAC 			Hashed Message Authentication Code
HUK 			Hardware Unique Key
Internal flash 	On-chip embedded flash
KDF 			Key Derivation Function
Manifest		Signed metadata for a firmware image
MCU 			Micro-controller unit
Measurement 	A cryptographic hash of code and/or data
MPU 			Memory Protection Unit
MTP 			Multi-Time Programmable. A characteristic of some type of NVM
NIST 			National Institute of Standards and Technology (http://www.nist.gov)
NSPE 			Non-Secure Processing Environment (a PSA term)
NSPE-PK 			Public Key of the Non-Secure Processing Environment
NVM 			Non-volatile memory
OEM 			Original Equipment Manufacturer
OTA 			Over-The-Air
OTP 			One Time Programmable. A characteristic of some types of NVM
PKI 			Public Key Infrastructure
PRoT 			PSA Root of Trust (a PSA term)
ROM 			Read-only memory
ROTPK 			Root of Trust Public Key (for firmware verification)
RSA 			Rivest, Shamir and Adleman. An algorithm for public-key cryptography.
RSA-PSS 		RSA Probabilistic Signature Scheme
Runtime 		firmware Generic term to describe the firmware that executes after boot has completed
SE 				Secure Element. An example of a secure element is a smart card.
SoC 			System on Chip
SPE 			Secure Processing Environment. Contains trusted firmware and trusted services.
SPE-PK 			Public Key of the Secure Processing Environment
System 			Inseparable component integrating all processing elements, bus masters, and secure software. Typically an SoC or equivalent

DEN0044Arm_Base_Boot_Requirements-1.0.pdf

>A64 The 		64-bit Arm instruction set used in AArch64 state. All A64 instructions are 32 bits.
AArch64 		state The Arm 64-bit Execution state that uses 64-bit general-purpose registers, and a 64-bit Program Counter (PC), Stack Pointer (SP), and Exception Link Registers (ELR). AArch64 Execution state provides a single instruction set, A64.
ACPI 			Advanced Configuration and Power Interface.
DT				DeviceTree
EFI 			Loaded Image An executable image to be run under the UEFI environment, and which uses boot time services.
EL0 			The lowest Exception level. The Exception level that is used to execute user applications, in Non-secure state.
EL1 			Privileged Exception level. The Exception level that is used to execute operating systems, in Non-secure state.
EL2 			Hypervisor Exception level. The Exception level that is used to execute hypervisor code. EL2 is always in Non-secure state.
EL3 			Secure monitor Exception level. The Exception level that is used to execute Secure monitor code, which handles the transitions between Non-secure and Secure states. EL3 is always in Secure state.
OEM 			Original Equipment Manufacturer. In this document, the final device manufacturer.
PSCI 			Power State Coordination Interface
SiP 			Silicon Partner. In this document, the silicon manufacturer.
SMBIOS 			System Management BIOS
SMCCC 			SMC Calling Convention
TCG 			Trusted Computing Group
TPM 			Trusted Platform Module
UEFI 			Unified Extensible Firmware Interface.
UEFI Boot Services -Functionality that is provided to UEFI Loaded Images during the UEFI boot process.
UEFI Runtime Services  -Functionality that is provided to an operating system after the ExitBootServices() call.

DEN0077A_Firmware_Framework_Arm_v8_A.pdf

>ABI				Application Binary Interface
DMA				Direct Memory Access
DSP				Digital Signal Processor
FF-A			Firmware Framework for A-profile
GIC				Generic Interrupt Controller
HVC				Hypervisor Call
MBP				Must be preserved
MBZ				Must be zero
MM				Management Mode
MMIO			Memory Mapped Input Output
MP				Multi-processing
OS				Operating System
PE				Processing Element
PPI				Private Peripheral Interrupt
PSA				Platform Security Architecture
SGI				Software Generated Interrupt

其它

type	title	reserved
AArch32 state	The ARM 32-bit Execution state that uses 32-bit general purpose registers, and a 32-bit program counter (PC), stack pointer (SP), and link register (LR). AArch32 Execution state provides a choice of two instruction sets, A32 and T32, previously called the ARM and Thumb instruction sets.	reserved
AArch64 state	The ARM 64-bit Execution state that uses 64-bit general purpose registers, and a 64-bit program counter (PC), stack pointer (SP), and exception link registers (ELR). AArch64 Execution state provides a single instruction set, A64.	reserved
EL0	The lowest Exception level. The Exception level that is used to execute user applications,in Non-secure state.	reserved
EL1	Privileged Exception level. The Exception level that is used to execute operating systems, in Non-secure state.	reserved
EL2	Hypervisor Exception level. The Exception level that is used to execute hypervisor code. EL2 is always in Non-secure state.	reserved
EL3	Secure Monitor Exception level. The Exception level that is used to execute Secure Monitor code, which handles the transitions between Non-secure and Secure states. EL3 is always in Secure state.	reserved
Function Identifier	A 32-bit integer that identifies which function is being invoked by this SMC or HVC call.Passed in R0 or W0 into every SMC or HVC call.	reserved
HVC	Hypervisor Call, an ARM assembler instruction that causes an exception that is taken synchronously into EL2.	reserved
Hypervisor	The hypervisor runs at the EL2 Exception level. It supports the execution of multiple EL1 Operating Systems.	reserved
Non-secure state	The ARM Execution state that restricts access to only the Non-secure system resources such as: memory, peripherals, and System registers.	reserved
OEM Original	Equipment Manufacturer. In this document, the final device manufacturer.PE Processing element. The abstract machine that is defined in the ARM architecture	reserved
Rx	Register; A32 native 32-bit register, A64 architectural register	reserved
S-EL0	The Secure EL0 Exception level, the Exception level that is used to execute trusted application code in Secure state	reserved
S-EL1	The Secure EL1 Exception level, the Exception level that is used to execute Trusted OS code in Secure state	reserved
Secure Monitor	The Secure Monitor is software that executes at the EL3 Exception level. It receives and handles Secure Monitor exceptions, and provides transitions between Secure state and Non-secure state	reserved
Secure state	The ARM Execution state that enables access to the Secure and Non-secure systems resources, such as: memory, peripherals, and System registers.	reserved
SiP	Silicon Partner，In this document, the silicon manufacturer.SMC Calling Convention Page 6 of 19 Copyright © 2013, 2016 ARM Limited or its affiliates. All rights reserved	reserved
SMC	Secure Monitor Call. An ARM assembler instruction that causes an exception that is taken synchronously into EL3	reserved
SMCCC	SMC Calling Convention, this document	reserved
SMC32/HVC32	32-bit SMC and HVC calling convention	reserved
SMC64/HVC64	64-bit SMC and HVC calling convention	reserved
Wx	A64 32-bit register view	reserved
Xx	A64 64-bit register view	reserved
Trusted OS	The secure operating system running in the Secure EL1 Exception level. It supports the execution of trusted applications in Secure EL	reserved
reserved	reserved	reserved

参考文献

DEN0077A_Firmware_Framework_Arm_v8_A.pdf
DEN0044Arm_Base_Boot_Requirements-1.0.pdf
Platform Security Boot Guide.pdf

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