verilog 之 流水灯实验

FPGA开发板：AX301:

板子芯片型号以及引脚设置

功能:4个灯 每隔一s轮流亮。

`timescale 1ns / 1ps
module led_test
(
	input           clk,           // system clock 50Mhz on board 时钟默认为50MHZ
	input           rst_n,         // reset ,low active
	output reg[3:0] led            // LED,use for control the LED signal on board
);

//define the time counter
//定义一个计数器
reg [31:0]      timer;

// cycle counter:from 0 to 4 sec
//50_000_000T == 1s
always@(posedge clk or negedge rst_n)
begin
	if (rst_n == 1'b0)
		timer <= 32'd0;                     //when the reset signal valid,time counter clearing
	else if (timer == 32'd199_999_999)      //4 seconds count(50M*4-1=199999999)
		timer <= 32'd0;                     //count done,clearing the time counter
	else
		timer <= timer + 32'd1;             //timer counter = timer counter + 1
end
//高电平有效
// LED control
always@(posedge clk or negedge rst_n)
begin
	if (rst_n == 1'b0)
		led <= 4'b0000;                     //when the reset signal active
	else if (timer == 32'd49_999_999)       //time counter count to 1st sec,LED1 lighten
		led <= 4'b0001;
	else if (timer == 32'd99_999_999)       //time counter count to 2nd sec,LED2 lighten
		led <= 4'b0010;
	else if (timer == 32'd149_999_999)      //time counter count to 3rd sec,LED3 lighten
		led <= 4'b0100;
	else if (timer == 32'd199_999_999)      //time counter count to 4th sec,LED4 lighten
		led <= 4'b1000;
end
endmodule

约束文件:

package require ::quartus::project
#clock 50m
set_location_assignment PIN_E1 -to clk
#key 
set_location_assignment PIN_N13 -to rst_n
set_location_assignment PIN_M15 -to key2
set_location_assignment PIN_M16 -to key3
set_location_assignment PIN_E16 -to key4
#led
set_location_assignment PIN_D9  -to led[3]
set_location_assignment PIN_C9  -to led[2]
set_location_assignment PIN_F9  -to led[1]
set_location_assignment PIN_E10 -to led[0]