LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY p_check IS
PORT(a: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
y: OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE behave OF p_check IS
BEGIN
PROCESS(a)
VARIABLE tmp:STD_LOGIC;
BEGIN
tmp := '0';
FOR n IN 0 TO 7 LOOP
tmp := tmp XOR a(n);
END LOOP;
y <= tmp;
END PROCESS;
END ARCHITECTURE;
利用FOR循环描述奇偶校验电路