linux arm 32 hard float abi,gcc softfp hard编译选项整理

ARM在使用gcc尤其是android编译中常常使用-mfloat-abi=softfp or -mfpu=fpv4-sp-d16，这两个选项具体是做什么用的呢？

想搞清楚就必须从ARM的EABI VFP和 NEON说起

ARM EABI

ARM EABI定义了ARM平台上编译器编译代码所使用的规则。对于ARM EABI来说有两种不兼容的ABIs:一个是使用floating-point registers作为函数参数，另外一种就是不使用。ARM有一个标准的floating-point指令集，虽然我们的硬件不支持，但是我们可以用来使用这个ABI。

Vector floating point(VFP)

VFP:ARM的浮点扩展，在armv8之前,VFP作为一个浮点协处理器扩展。在armv8中VFP已经被NEON所取代。对于ARM来说VFP 扩展知识optional部分。比如cortex-A8 只有cut-down VFPLite而不是一个full VFP moudle,下面是VFP的各个版本号

VFPv1

Obsoleted by ARM

VFPv2

16 64-bit FPU registers

Optional extension to the ARM instruction set in the ARMv5TE, ARMv5TEJ, ARMv6, and ARMv6K architectures

Optional extension to the ARM and Thumb instruction set in the ARMv6T2 architecture

Supports standard FPU arithmetic (add, sub, neg, mul, div), full square root

VFPv3

Backwards compatible with VFPv2, except that it cannot trap floating-point exceptions

Adds VCVT instructions to convert between scalar, float and double

Adds immediate mode to VMOV such that constants can be loaded into FPU registers.

VFPv3-D32

32 64-bit FPU registers

Implemented on most Cortex-A8 and A9 ARMv7 processors

VFPv3-D16

16 64-bit FPU registers

Implemented on Cortex-R4 and R5 processors and the Tegra 2 (Cortex-A9).

VFPv3-F16

Uncommon

Supports IEEE754-2008 half-precision (16-bit) floating point as a storage format

VFPv3U

A variant of VFPv3 that supports the trapping of floating-point exceptions to support code.

Can support single- or half-precision floating point

VFPv4

Built on VFPv3

Adds half-precision support as a storage format

Adds fused multiply-accumulate instructions

VFPv4-D32

32 64-bit FPU registers

Implemented on the Cortex-A12 and A15 ARMv7 processors

Cortex-A7 optionally has VFPv4-D32 (in the case of an FPU with NEON)

VFPv4-D16

16 64-bit FPU registers

Implemented on Cortex-A5 and A7 processors (in case of an FPU without NEON)

VFPv4U

A variant of VFPv4 that supports the trapping of floating-point exceptions to support code

Can support single- or half-precision floating point

VFPv5

Implemented on Cortex-M7 when single and double-precision floating-point core option exists

NEON

NEON：the Andvanced Single Instruction Multiple Data(SIMD) Extension, NEON是ARM VFP协处理器的继承者。在ARMV8之前，VFP和NEON对于浮点的支持是不同的，NEON不是IEE754兼容性，有一些VFP支持的指令而NEON不支持，但是从ARMV8之后，这种情况就不存在了。在Cortex-a8中，NEON是都包含的。

compiler选项

-mfloat-abi= 后面的参数

soft: full software floating-point support

softfp: Allows use of floating-point instructions but maintains compatibility with the soft-float ABI

hard: Uses floating-point instructions and the floating-point ABI.

同一个program只能使用一种

FPU

当使用hard或者softfp float-abi是，必须同时指定FPU,

The -mfpu= option supports the following FPU types: vfp, vfpv3, vfpv3-fp16, vfpv3-d16, vfpv3-d16-fp16, vfpv3xd, vfpv3xd-fp16, neon, neon-fp16, vfpv4, vfpv4-d16, fpv4-sp-d16, neon-vfpv4, fp-armv8, neon-fp-armv8, and crypto-neon-fp-armv8.

FP16-FORMAT

The-mfp16-format= option allows you to specify the format of the half-precision floating-point type (__fp16). Valid options are none, ieee, and alternative. The default option is none, meaning __fp16 is not defined.