SMPTE协议解读

SMPTE 292M 1998
本协议定义HDSDI标准。

SAV---- start of active video,
EAV---- end of active video,
LN---- line number,
CRC ----校验数据
Digital Active Line ---- 行内有效数据
Digital Line Blanking---- 行内留白数据
HANC---- data between EAV and SAV
VANC----

EAV是由
0x3FF+0x000+0x000+XYZ构成。
SAV是由
0x3FF+0x000+0x000+XYZ构成。
LN是由
LN0+LN1构成。
CRC是由
YCRC0+YCRC1构成。

可见，EAV和SAV的区分，是由XYZ的值来区分的。
SAV的合法值:
0x200---- during field 0, at field 0 elsewhere,(not at field 0 vblanking), in SAV
0x2ac---- during field 0, at field 0 vblanking, in SAV
0x31c---- during field 1, at field 1 elsewhere,(not at field 1 vblanking), in SAV
0x3b0---- during field 1, at field 1 vblanking, in SAV

EAV的合法值：
0x274----during field 0, at field 0 elsewhere,(not at field 0 blanking), in EAV
0x2d8---- during field 0, at field 0 blanking, in EAV
0x368----during field 1, at field 1 elsewhere,(not at field 1 blanking), in EAV
0x3c4----during field 1, at field 1 blanking, in EAV

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SMPTE 274M
本协议定义Video standard。1920x1080.

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SMPTE 296M
本协议定义Video standard。1280x720.

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SMPTE 424M
本协议定义3GSDI标准。

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SMPTE 352
本协议定义vpid。

Byte 1: Video payload standard
the first byte can be used to address up to 255 valid video payload standards.
ancillary data with a DIDrange of
88h – 9Fh
must be considered as data start marker packets
Data count for this packet is set to zero (0) 。
ancillary data with a DID
range of
84h – 87h
must be considered as data end marker packets
Data count for this packet is set to zero (0) 。

Presently unassigned type 1 DID codes (in 8-bit ID format):
81h through 83h (reserved);
85h through 87h (reserved);
89h through 9Fh (reserved).

Byte 2: Video payload frame rate and line scanning
For all video payloads on SDI transports, bits b3 to b0 of byte 2 shall be reserved to define the video frame rate in hertz. The 4 bits allow values of 0h to Fh which shall be as defined in table 1.
Bits b7 and b4 are used as defined by the application. The default value of these bits shall be 0.

2h---- 24/1.001
3h ----24

5h ----25
6h ----30/1.001
7h ----30

9h ----50
Ah ----60/1.001
Bh ----60

Dh ----75
Eh ----72/1.001
Fh ----72

Bits b7 and b6 of byte 2 shall define a number to identify
the scanning format.
0h = Interlace (I).
1h = Segmented frame (PsF).
3h = Progressive §.
The value 2h is reserved,

Byte 3: Sampling structures
For all video payloads on SDI transports, bits b3 to b0 of byte 3 shall be reserved to identify the horizontal sampling structure. The 4 bits allow values of 0h to Fh which shall be as defined in table 2.
0h ----4:2:2 I (4:3)
1h ----4:2:2 I (16:9)
2h ----4:2:0 P (4:3)
3h ----4:2:2 P (4:3,dual link)
4h ----4:2:2 P (4:3)
5h ----4:2:2 P (16:9)
6h ----4:4:4:4 I (4:3,Y/Cb/Cr/key)
7h ----4:4:4:4 I (4:3,R/G/B/key)
8h ----4:2:2 I (4:3,dual channel)
9h ----4:2:2 I (16:9,dual channel
Ah ----4:2:0 P (4:3,dual channel)

Fh ----4fsc

Byte 4: Special options
A null value in byte 4 [00h] shall be used to indicate either no useful data or the default case

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pg071是SMPTE-SDI核的手册。

The SDI receiver has an automatic transport format detector.
This function determines the transport format, not the picture format.
For example, when 1080p 60 Hz video is transported on
3G-SDI level B-DL, the video transport is actually 1080i 60 Hz - the transport is interlaced,
but the picture is progressive.

The transport detection unit also determines whether transport is interlaced or
progressive and reports this on the rx_t_scan output port.

This automatic SDI mode detection feature can be disabled by driving the
rx_mode_detect_en input port Low.

when using a Xilinx transceiver to receive SD-SDI, the transceiver is
locked to its reference clock and oversamples the SD-SDI bit stream by a factor of 11X.
A data recovery unit (DRU) is implemented in
the fabric of the FPGA to recover the SD-SDI data from the oversampled data output by the
transceiver.
The 10-bit data stream from the DRU must be connected to the rx_sd_data_in port of the SMPTE SD/HD/3G-SDI core.
This data ready signal from the DRU must be connected to the rx_sd_data_strobe input of the SMPTE
SD/HD/3G-SDI core.

When the SDI receiver is operating in HD-SDI mode,
The Y and C data streams of the HD-SDI signal are output on the rx_ds1a and rx_ds2a ports, respectively, along with the timing signals
rx_trs, rx_eav, rx_sav.
The line number is output on the
rx_line_a.
In HD-SDI mode, the line number changes during the CRC0 word.

When the 3G-SDI level B signal carries two independent HD-SDI streams (level B-DS), the
first HD-SDI stream is output with the luma component on rx_ds1a and the multiplexed
chroma components on rxds2a. The second HD-SDI stream is output with the luma
component on rx_ds1b and the multiplexed chroma component on rx_ds2b.
These two HD-SDI streams are horizontally synchronized such that their EAVs and SAVs always line up
exactly, therefore there is only a single set of rx_eav, rx_sav, and rx_trs timing signals.

The receiver in the SMPTE SD/HD/3G-SDI core captures SMPTE ST 352 packets present in
the data streams for all SDI modes.
For SD-SDI and HD-SDI modes, the four data bytes of
the ST 352 packet are output on the
rx_a_vpid port.

The rx_a_vpid_valid
portindicates when valid ST 352 packets have been captured.

The 3G-SDI standard requires ST 352 packets in both data streams. The SDI receiver
captures the ST 352 packets from both streams, outputting the data from the packet in data
stream 1 on rx_a_vpid, and the data from the packet in data stream 2 on rx_b_vpid. The
module also supplies individual rx_a_vpid_valid and rx_b_vpid_valid outputs.

The SDI mode (SD-SDI, HD-SDI, 3G-SDI level A or 3G-SDI level B) of the SDI transmitter is
determined by the tx_mode and tx_level_b_3g inputs.

The interleaved Y/C data stream is connected to the tx_video_a_y_in port of the
SMPTE SD/HD/3G-SDI core. The tx_ce clock enable input of SMPTE SD/HD/3G-SDI core
must be asserted at a 27 MHz rate,
This means that tx_ce must be asserted with a 5/6/5/6 clock cycle cadence.
The tx_din_rdy port must always be held High in SD-SDI mode.

the tx_ce port of the SMPTE SD/HD/3G-SDI core is three bits wide. All three bits
must be driven with duplicate copies of the clock enable signal.
the firstword of the EAV is a 5-clock cycle sample, there is no such relationship required. The first word of the EAV could instead be a 6-clock cycle sample.

In SD-SDI mode, the line number value on the tx_line_a input port is only used to insert ST 352 packets.
If ST 352packet insertion is disabled (tx_insert_vpid is Low), then line numbers are not required on the
tx_line_a
port inSD-SDI mode.
When used, the line number on tx_line_a must be stable starting with the XYZ word of the EAV, and must remain valid through the entire HANC interval. The VPID data bytes also have the same timing requirementsas tx_line_a.

When operating in HD-SDI mode, The tx_ce and tx_din_rdy input ports must always be High.
HD video enters the SMPTE SD/HD/3G-SDI core as two 10-bit data streams with the Y data
stream on the tx_video_a_y_in port and the C data stream on the tx_video_a_c_in port.
If the tx_insert_vpid input is High, ST 352 packets are generated and inserted.
The SMPTE SD/HD/3G-SDI core inserts line numbers into both data streams immediately
after the EAV, if tx_insert_ln is High. It calculates and inserts CRC values immediately
after the line numbers if tx_insert_crc is High.

It scrambles the data streams and outputs one 20-bit data stream running at 74.25 MHz or 74.25/1.001 MHz on the tx_txdata output port.
Line numbers must be supplied on the tx_line_a port if either ST 352 packet insertion or
line number insertion are enabled.

In HD-SDI mode, the line number value on the tx_line_a input port must be stable starting with the XYZ word of the EAV, and must remain valid through the entire HANC interval.
The VPID input bytes must be stable beginning with the XYZ word of the EAV, and must remain stable during the entire HANC interval on lines where SMPTE ST 352 packets are inserted.

When operating in 3G-SDI mode, the transmitter can operate in level A mode or level B
mode, as selected by the tx_level_b_3g input (level A = Low, level B = High)

In 3G-SDI level A mode, the SMPTE SD/HD/3G-SDI core requires two 10-bit data streams on
the tx_a_y_in (data stream 1) and tx_a_c_in (data stream 2) input ports.
The tx_ce and tx_din_rdy inputs must always be High.

In 3G-SDI level A mode, the line number value on the tx_line_a input port must be stable starting with the XYZ wordof the EAV, and must remain valid through the entire HANC interval.
The VPID input bytes must be stable beginning with the XYZ word of the EAV, and must remain stable during the entire HANC interval on lines where SMPTE ST 352 packets are inserted.

The SDI transmitter inserts the line number on the tx_line_a port into both data streams
immediately after the EAV, if tx_insert_ln is High. It calculates and inserts CRC values
immediately after the line numbers, if tx_insert_crc is High. It scrambles the data
streams and outputs one 20-bit data stream running at 148.5 MHz on the tx_txdata
output port。

Line numbers are required on the tx_line_a port if either ST 352 packet insertion or line
number insertion are enabled。

When running in 3G-SDI level B mode, the SMPTE SD/HD/3G-SDI core requires four 10-bit
data streams on its tx_video_a_y_in (Y channel of link A), tx_video_a_c_in (C
channel of link A), tx_video_b_y_in (Y channel of link B), and tx_video_b_c_in (C
channel of link B) ports.

Thus, in 3G-SDI B mode, the correct way to control the data rate of the SDI transmitter is to keep tx_ce High and toggle the tx_din_rdy signal every other clock cycle

In 3G-SDI mode, the line number values on the tx_line_a and tx_line_b input ports must be stable starting with the XYZ word of the EAV, and must remain valid through the entire HANC interval.
The VPID input bytes must be stable beginning with the XYZ word of the EAV, and must remain stable during the entire HANC interval on lines where ST 352 packets are inserted.

If tx_insert_ln is High, the transmitter inserts line numbers into all four data streams. If
tx_insert_crc is High, it calculates and inserts CRC values immediately after the line
numbers in all four data streams. The data streams are then interleaved to produce a single
20-bit data stream running at 148.5 MHz or 148.5/1.001 MHz on the tx_txdata output
port.

The ST 352 packet insertion function takes the user data words of the ST 352 packet from
the VPID input ports: tx_vpid_byte1, tx_vpid_byte2, tx_vpid_byte3, tx_vpid_byte4a, and tx_vpid_byte4b.
The tx_vpid_byte4b port is only used in
3G-SDI mode to allow unique identification between the two data streams carried on the
3G-SDI interface.

The ST 352 packet will be insertedat the beginning of the HANC space of the line specified by the tx_line_f1
input port for progressive video or for the first field of interlaced video. For interlaced video, a ST 352 packet is also inserted on the line specified by the
tx_line_f2
input port.

The
tx_line_f2_en
input determines whether packets are inserted in the line specified by
tx_line_f2.
The
tx_line_f2_en
input must be Low for a progressive transport and High for an interlaced transport.This input must be High for interlaced video and Low for progressive video.

When running in SD-SDI mode, the SDI transmitter generates
and inserts EDH packets when tx_insert_edh is High.

The data streams containing the ST 352 packets are output on the tx_dsxx_out ports to feed to the
ancillary data inserter. The data streams from the ancillary data inserter must be connected
to the core’s tx_dsxx_in ports of the core.

The signal on the rx_rst input port must be synchronous with the rx_usrclk clock.
The signal on the tx_rst input port must be synchronous with the tx_usrclk clock.