rk3128有多少个bank_瑞芯微RK3128芯片简介

瑞芯微RK3128芯片简介，RK3128是一款高性价比的通用型SoC，非常适合大规模部署的项目。RK3128官方支持安卓系统，有第三方的Linux系统，目前主要用于数字标牌、平板电脑等产品。

RK3128 is a high performance Quad-core application processor for smart TV-Box. Especially it is a high-integration and cost efficient SOC for 1080P H.265 TV-Box.

Quad-core Cortex-A7 is integrates with separately Neon and FPU coprocessor. Mali400 MP2 GPU is embedded to support smoothly high-resolution (1080p) display and mainstream game.

Lots of high-performance interface to get very flexible solution, such as multi-pipe display with HDMI1.4, TV Encoder. Crypto hardware is integrated for support security BOOT. 32bits DDR3/LPDDR2 provides high memory bandwidths for high-performance.

HEVC hardware is integrated for support 1080P H.265 video.

1.1  Features

1.1.2  Microprocessor

Quad-core ARM Cortex-A7MP Core processor, a high-performance, low-power and cached application processor

Full implementation of the ARM architecture v7-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation

Separately Integrated Neon and FPU per CPU

32KB/32KB L1 I-Cache/D-Cache per

Unified 256KB L2

1.1.3  Memory Organization

Internal on-chip memory

BootRom

Internal SRAM

External off-chip memory①

DDR3/DDR3L/LPDDR2

Async/Toggle/SyncNand Flash(include LBA Nand)

1.1.4  Internal Memory

Internal BootRom

Support system boot from the following device :

8bits Async Nand Flash

8bits toggle Nand Flash

SPI interface

eMMC interface

SDMMC interface

Support system code download by the following interface:

USB OTG interface

Internal SRAM

Size : 8KB

1.1.5  External Memory or Storage device

Dynamic Memory Interface (DDR3/DDR3L/LPDDR2)

Compatible with JEDEC standard DDR3-1066/DDR3L-1066/LPDDR2-800 SDRAM

Supports 32 Bits data width, 2 ranks (chip selects), totally 2GB (max) address

7 host ports with 64bits/128bits AXI bus interface for system access, AXI bus clock

is asynchronous with DDR clock

Programmable timing parameters to support DDR3/DDR3L/LPDDR2 SDRAM from various vendor

Advanced command reordering and scheduling to maximize bus utilization

Low power modes, such as power-down and self-refresh for DDR3/LPDDR2 SDRAM; clock stop and deep power-down for LPDDR2 SDRAM

Compensation for board delays and variable latencies through programmable pipelines

Programmable output and ODT impedance with dynamic PVT compensation

Nand Flash Interface

Support 8bits async/toggle/syncnandflash, up to 4 banks

Support LBA nandflash

16bits, 24bits, 40bits, 60bits hardware ECC

For DDR nandflash, support DLL bypass and 1/4 or 1/8 clock adjust

For async/togglenandflash, support configurable interface timing, maximum data rate is 16bit/cycle

Embedded AHB master interface to do data transfer by DMA method

Also support data transfer by AHB slave interface together with external DMAC

eMMC Interface

Compatible with standard iNAND interface

Support MMC4.5 protocol

Provide eMMC boot sequence to receive boot data from external eMMC device

Support FIFO   over-run   and   under-run   prevention   by   stopping  card   clock automatically

Support CRC generation and error detection

Embedded clock frequency division control to provide programmable baud rate

Support block size from 1 to 65535Bytes

8bits data bus width

SD/MMC Interface

Compatible with SD2.0, MMC ver 5

Support FIFO   over-run   and   under-run   prevention   by   stopping  card   clock automatically

Support CRC generation and error detection

Embedded clock frequency division control to provide programmable baud rate

Support block size from 1 to 65535Bytes

Data bus width is 4bits

1.1.6  System Component

CRU (clock & reset unit)

Support clock gating control for individual components inside RK3128

One oscillator with 24MHz clock input and 4 embedded PLLs

Support global soft-reset control for whole SOC, also individual soft-reset for every components

PMU(power management unit)

Multiple configurable work modes to save power by different frequency or automatically clock gating control or power domain on/off control

Lots of wakeup sources in different mode

2 separate voltage domains

3 separate power domains, which can be power up/down by software based on different application scenes

Timer

6 on-chip 64bits Timers in SoC with interrupt-based operation

Provide two operation modes: free-running and user-defined count

Support timer work state checkable

Fixed 24MHz clock input

PWM

Four on-chip PWMs with interrupt-based operation

Programmable pre-scaled operation to bus clock