HLS ug871学习

Interface

lab1

IO blcok protocol
ap_ctrl_none

lab2

No IO protocol. This is the default for inputs
ap_vld: Implemented with an associated output valid port. This is
the default for outputs
ap_ack: Implemented with an associated input acknowledge port

lab3

The d_o argument has been synthesized to a RAM port (IO protocol ap_memory).
o A data port (d_o_d0).
o An address port (d_o_address0).
o Control ports for chip-enable (d_o_ce0) and a write-enable port (do_we0)
• The d_i argument has been synthesized to a similar RAM interface, but has an input data
port (d_i_q0) and no write-enable port since this interface only reads data

Partitioned 分区的
unroll 展开

directive 为ram fifo资源啥的

可以选择

lab4

array partition
添加axi 总线形式