Verilog
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synthesizable之Verilog可不可综合
(1)所有综合工具都支持的结构:always,assign,begin,end,case,wire,tri,aupply0,supply1,reg,integer,default,for,function,and,nand,or,nor,xor,xnor,buf,not,bufif0,bufif1,notif0,notif1,if,inout,input,instantitation,module,negedge,posedge,operators,output,parameter。(2)所有综合工具都不原创 2022-07-12 10:31:59 · 1262 阅读 · 0 评论 -
Verilog 刷题 day2
1.Vector0Vectors are used to group related signals using one name to make it more convenient to manipulate. For example, wire [7:0] w; declares an 8-bit vector named w that is functionally equivalent to having 8 separate wires.解答:module top_module (原创 2021-12-21 23:02:37 · 703 阅读 · 0 评论 -
Verilog刷题day1
Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).建立一个没有输入和一个输出的电路。该输出应始终驱动 1(或逻辑高)。题目:module top_module( output one );// Insert your code here assign one = [fixme];endmodule解答:module top_m原创 2021-12-20 10:53:32 · 2104 阅读 · 1 评论