Verilog 刷题 day2

1.Vector0

Vectors are used to group related signals using one name to make it more convenient to manipulate. For example, wire [7:0] w; declares an 8-bit vector named w that is functionally equivalent to having 8 separate wires.

解答：

module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0  ); // Module body starts after module declaration
    assign outv[2:0]=vec[2:0];
    assign o0=vec[0],o1=vec[1],o2=vec[2];
endmodule

结果：

这里是用数列的意思

2.Vector1

课前学习内容
Accessing Vector Elements: Part-Select
Accessing an entire vector is done using the vector name. For example:

assign w = a;
takes the entire 4-bit vector a and assigns it to the entire 8-bit vector w (declarations are taken from above). If the lengths of the right and left sides don’t match, it is zero-extended or truncated as appropriate.
The part-select operator can be used to access a portion of a vector:

w[3:0] // Only the lower 4 bits of w
x[1] // The lowest bit of x
x[1:1] // …also the lowest bit of x
z[-1:-2] // Two lowest bits of z
b[3:0] // Illegal. Vector part-select must match the direction of the declaration.
b[0:3] // The upper 4 bits of b.
assign w[3:0] = b[0:3]; // Assign upper 4 bits of b to lower 4 bits of w. w[3]=b[0], w[2]=b[1], etc.

题目：

Build a combinational circuit that splits an input half-word (16 bits, [15:0] ) into lower [7:0] and upper [15:8] bytes.

解答：

`default_nettype none     // Disable implicit nets. Reduces some types of bugs.
module top_module( 
    input wire [15:0] in,
    output wire [7:0] out_hi,
    output wire [7:0] out_lo );
    
    assign out_hi[7:0]=in[15:8];
    assign out_lo[7:0]=in[7:0];
    
endmodule

结果：

这里用了
`default_nettype none // Disable implicit nets. Reduces some types of bugs.
这句是显示Implicit nets，出现错误时会提醒

3.Vector2

A 32-bit vector can be viewed as containing 4 bytes (bits [31:24], [23:16], etc.). Build a circuit that will reverse the byte ordering of the 4-byte word.

AaaaaaaaBbbbbbbbCcccccccDddddddd => DdddddddCcccccccBbbbbbbbAaaaaaaa
This operation is often used when the endianness of a piece of data needs to be swapped, for example between little-endian x86 systems and the big-endian formats used in many Internet protocols.

题目：
调节4字节节序的代码

解答：

module top_module( 
    input [31:0] in,
    output [31:0] out );//

    assign out[31:0] = {in[7:0],in[15:8],in[23:16],in[31:24]};

endmodule

结果：

4. Vectorgates

Build a circuit that has two 3-bit inputs that computes the bitwise-OR of the two vectors, the logical-OR of the two vectors, and the inverse (NOT) of both vectors. Place the inverse of b in the upper half of out_not (i.e., bits [5:3]), and the inverse of a in the lower half.

解答：

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);

    assign out_or_bitwise[2:0]=a[2:0]|b[2:0];
    assign out_or_logical=a||b;
    assign out_not[5:0]={~b[2:0],~a[2:0]};
    
endmodule

结果：

5.Gates4

Build a combinational circuit with four inputs, in[3:0].

There are 3 outputs:

out_and: output of a 4-input AND gate.
out_or: output of a 4-input OR gate.
out_xor: output of a 4-input XOR gate.
To review the AND, OR, and XOR operators, see andgate, norgate, and xnorgate.
解答：

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);
    assign out_and=in[3]&&in[2]&&in[1]&&in[0];
    assign out_or=in[0]||in[1]||in[2]||in[3];
    assign out_xor=in[0]^in[1]^in[2]^in[3];
endmodule

结果：

6.Vector3

Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, d, e, and f, for a total of 30 bits of input. There are four 8-bit output vectors: w, x, y, and z, for 32 bits of output. The output should be a concatenation of the input vectors followed by two 1 bits:

解答：

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );
    
    wire [31:0]Med;
    
    assign Med={a,b,c,d,e,f,2'b11};
    assign {w}={Med[31:24]};
    assign {x}={Med[23:16]};
    assign {y}={Med[15:8]};
    assign {z}={Med[7:0]};
   // assign {w,x,y,z}={a,b,c,d,e,f,2'b11};
endmodule

结果：

哈哈哈哈哈，这个地方有点傻了，请看注释内的代码更加简单

7.Vectorr

Given an 8-bit input vector [7:0], reverse its bit ordering.反位

解答：

module top_module( 
    input [7:0] in,
    output [7:0] out
);
    assign out[7] = in[0];
    assign out[6] = in[1];
    assign out[5] = in[2];
    assign out[4] = in[3];
    assign out[3] = in[4];
    assign out[2] = in[5];
    assign out[1] = in[6];
    assign out[0] = in[7];
    
endmodule

结果：

法二：

module top_module( 
    input [7:0] in,
    output [7:0] out
);
    //assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};
	/*
    integer i;
    always @(*)
        for(i=0;i<=7;i= i+1)
            begin
                out[i] = in [7-i]; 
            end
    */
  	generate         
       genvar i;
        for(i=0;i<=7;i=i+1)
            begin:
               conv
                assign out[i] = in[7-i];
            end
    endgenerate
endmodule

法二更加技术化，
另外不行的办法：assign out[7:0] = in[0:7];
does not work because Verilog does not allow vector bit ordering to be flipped.

8.Vector4

题目：
Build a circuit that sign-extends an 8-bit number to 32 bits. This requires a concatenation of 24 copies of the sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit number itself.

解答：

module top_module (
    input [7:0] in,
    output [31:0] out );//

    assign out = {{24{in[7]}},in};

endmodule

课后知识：

Examples:

{5{1’b1}} // 5’b11111 (or 5’d31 or 5’h1f)
{2{a,b,c}} // The same as {a,b,c,a,b,c}
{3’d5, {2{3’d6}}} // 9’b101_110_110. It’s a concatenation of 101 with
// the second vector, which is two copies of 3’b110.
For example, sign-extending 4’b0101 (5) to 8 bits results in 8’b00000101 (5), while sign-extending 4’b1101 (-3) to 8 bits results in 8’b11111101 (-3).

9.Vector5

Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise one-bit comparisons in the 25-bit output vector. The output should be 1 if the two bits being compared are equal.

out[24] = ~a ^ a; // a == a, so out[24] is always 1.
out[23] = ~a ^ b;
out[22] = ~a ^ c;
…
out[ 1] = ~e ^ d;
out[ 0] = ~e ^ e;
题目：

As the diagram shows, this can be done more easily using the replication and concatenation operators.

The top vector is a concatenation of 5 repeats of each input
The bottom vector is 5 repeats of a concatenation of the 5 inputs

解答：

module top_module (
    input a, b, c, d, e,
    output [24:0] out );//

    // The output is XNOR of two vectors created by 
    // concatenating and replicating the five inputs.
    assign out = ~{{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}} ^ {{5{a,b,c,d,e}}};

endmodule

加油！