网址:https://hdlbits.01xz.net/wiki/Edgedetect
module top_module (
input clk,
input [7:0] in,
output [7:0] pedge
);
reg [7:0] r_in;
always
网址:https://hdlbits.01xz.net/wiki/Edgedetect
module top_module (
input clk,
input [7:0] in,
output [7:0] pedge
);
reg [7:0] r_in;
always