1.建立modelsim.bat文件
vsim -do sim.do
2.建立sim.do文件
vlog +incdir+ ./../src/video_process_top/vga_ctr.v \
./sim_tb.v
vsim -novopt +nowarnPCDPC -L ecp3 -t 1ns work.sim_tb
view structure
view signals
view wave
radix -decimal
add wave -noupdate -divider {Global Signals}
add wave -noupdate -format Logic /sim_tb/U0_vga_ctr_inst/*
run 3ms
modelsim调试时,将需要查看的信号拉在一起并排序,若需要重新仿真,可直接选择信号复制黏贴到do文件中,前面加上add wave -dev ,就可以在重新仿真出来的波形中直接看到需要查看的信号及其排序
3.建立sim_tb.v文件
`timescale 1 ns / 100 ps
module sim_tb();
reg clk;
reg rst_n;
wire sof_test;
wire eof_test;
wire sol_test;
wire eol_test;
wire valid_test;
wire [23:0] dout_test;
vga_ctr U0_vga_ctr_inst(
.rst_n (rst_n ),
.vid_clk (clk ),
.sof (sof_test ),
.eof (eof_test ),
.sol (sol_test ),
.eol (eol_test ),
.dout_valid (valid_test ),
.dout (dout_test )
);
initial
begin
clk = 1'd1;
rst_n = 1'd0;
#1000 rst_n = 1'd1;
end
always
begin
#10 clk = ~clk;
end
endmodule
4.常用modelsim命令
quit -sim 不需要执行,可直接执行do sim.do
do sim.do
run 3ms
5.编译lattice器件库
①在X:\modeltech_10.0c下建立文件夹Lattice
②去掉modelsim安装根目录下modelsim.ini的只读属性
③打开modelsim,File >> change directory,选择新建的文件夹“Lattice”
④若为ECP3器件, File >> New >> Library中的Library Name中输入ECP3
(选项为a new library and a logical mapping to it)
⑤Compile >> Compile,库选择ECP3,文件选择X:\lscc\diamond\3.9\cae_library\simulation\verilog下的ecp3和pmi中的所有文件进行编译,无报错即可
⑥打开modelsim.ini,会发现有一行:ECP3 = ECP3,修改为ECP3 = X:\modeltech_10.0c\Lattice\ECP3即可;
⑦增加modelsim.ini只读属性即可
6.lattice modelsim仿真时调用IP仿真报错
# ELAB2: Fatal Error: ELAB2_0036 Unresolved hierarchical reference to “PUR_INST.PURNET”
from module “FifoTest_tb.rom.rom_0_3” (module not found).
ELAB2: Fatal Error: ELAB2_0036 Unresolved hierarchical reference to “PUR_INST.PURNET”
from module “FifoTest_tb.fifo.FifoMacro_0_3” (module not found).
问题解决,在仿真tb顶层文件中加
GSR GSR_INST (.GSR (1’b1));
PUR PUR_INST (.PUR (1’b1));即可