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原创 序列信号发生器,之D触发器异步复位和异步置位
本来只想做一下序列信号发生器的手撕代码,但是综合之后看了一下生成的原理图,觉得无法理解,就研究了一下。 序列信号发生器很简单,我用移位实现的,代码如下module xuliexinhao( input sys_clk, //时钟 input sys_rst_n, //复位,低有效 input [9:0] in, //待输出序列 output reg out //输出 );reg [9:0] data;alw...
2021-12-17 11:11:45 9365
原创 HDL Bits刷题记录,counter1000,1Hz计数器
From a 1000 Hz clock, derive a 1 Hz signal, calledOneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, theOneHertzsignal...
2021-11-10 11:04:11 739
原创 HDL Bits刷题记录,Edgecapture下降沿监测
For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (synchronous reset).hint:当下降沿和复位同时到达时,复位优先级高于下降沿。module top_modu.
2021-11-09 19:51:23 210
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