GPIO 在不同平台的地址

一、以酷睿平台为例
访问GPIO 按如下公式
每个GPIO都有单独的地址 和32bit配置空间

SBREG_BAR 在代码中宏定义可以找到
port id 需要查询EDS Vol1

二、以至强平台为例
所有的GPIO配置信息压缩在几个寄存器中
7.10 General Purpose I/O Registers
The control for the general purpose I/O signals is handled through a 128-byte I/O
space. The base offset for this space is selected by the GPIOBASE register.
GPIO base address 通过PCIE B D F即可获得

配置空间解读：
例如
GPIO_USE_SEL
Each bit in this register enables the corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native function. 0 = Signal used as native function. 1 = Signal used as a GPIO.（native应该表示改gpio可以复用 eds GPIO signals或者 general purpose I/O signals可以查到对应的复用功能）

GPIO0 被用作GPIO, 那么GPIO_USE_SEL的bit0 为1
同理 GPIO1被设置为native 那么GPIO_USE_SEL的bit1 为0.
GPIO_USE_SEL只有32 bit 可以被用作32个GPIO 的use select配置。
那么超过32之外的GPIO怎么配置呢，我们看到GPIO_USE_SEL2和GPIO_USE_SEL3
32到63的GPIO用sel2寄存器 64以上的用 sel3寄存器

其他GPIO 配置属性：
1）GP_IO_SEL 0 = Output. The corresponding GPIO signal is an output. 1 = Input. The corresponding GPIO signal is an input. 值得注意的是When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have no effect.
2）GP_LVL If GPIO[n] is programmed to be an output (using the corresponding bit in the GP_IO_SEL register), then the corresponding GP_LVL[n] write register value will drive a high or low value on the output pin. 1 = high, 0 = low. 只有设定为output的时候 此bit生效
3）GPI_INV This bit only has effect if the corresponding GPIO is used as an input and used by the GPE logic, where the polarity matters. When set to ‘1’, then the GPI is inverted as it is sent to the GPE logic that is using it. This bit has no effect on the value that is reported in the GP_LVL register.

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