1. Vivado建立工程,要保证和硬件匹配,不然加载overlay会导致原有配置被覆盖,出现接口失效、死机等问题(最好在pynq系统构建时用的hdf的项目基础上进行扩展)
2. 完成ip设计后先 Generate Block Design完成综合、实现,之后Generate Bitstream 生成字节流,之后 Create HDL Wrapper 才会更新tcl,之后就可以在File栏下导出bit 和 tcl进行使用
3. dma回环测试代码
import numpy as np
from pynq import Xlnk
from pynq import Overlay
import time
ol = Overlay('zynq.bit')
dma = ol.axi_dma_0
xlnk = Xlnk()
input_buffer = xlnk.cma_array(shape=(6553600,), dtype=np.uint32)
output_buffer = xlnk.cma_array(shape=(6553600,), dtype=np.uint32)
start = time.time()
dma.sendchannel.transfer(input_buffer)
dma.recvchannel.transfer(output_buffer)
dma.sendchannel.wait()
dma.recvchannel.wait()
end = time.time()
print('time cost ' + str(round(end - start, 5)) + 's')
length = 26214400
cost = round(end - start, 5)
speed = round(length/(cost*1048576),5)
print('transfer speed: ' + str(speed) + 'MB/s')