Verilog-asm小练习—PLL建模

最新推荐文章于 2023-08-06 15:44:07 发布

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最新推荐文章于 2023-08-06 15:44:07 发布

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本文链接：https://blog.csdn.net/weixin_44700185/article/details/128841268

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该文描述了一个锁相环(PLL)的VerilogAMS实现，包括相位频率检测器(PFD)，电荷泵(CP)，电容，电阻和压控振荡器(VCO)模块。系统还包含了数字延迟线(FD)用于反馈。VCO的设计考虑了频率调制和rin参数的影响。

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`include "discipline.vams"
`timescale 10ps/1ps
module pll_top;
    electrical gnd;
    ground     gnd;
    reg        ref,reset;

initial begin
    ref=0;
    reset=1;
    #100 reset=0;
end

always #3333 ref=~ref;

pfd PFD(.reset(reset),.qinc(up),.active(fb),.ref(ref),.qdec(qdec));
cp #(.cur(1m)) CP(.nout(gnd),.dec(dwn),.inc(up),.pout(err));
capacitor #(.c(30n)) C(err,err2);
resister #(.r(200)) R(err,gnd);
vco #(.f0(1.5E9),.kvco(50.0E6),.rin(100k)) VCO(.ps(err),.ns(gnd),.out(out));
fd FD(.reset(reset),.out(fb),.clk(out));
endmodule

// .........................................PFD PFD PFD..................
module pfd(reset,qinc,active,ref,qdec)
output qinc,qdec;
input  reset,active,ref
wire fv_rst,fr_rst;
reg out0,out1;
assign fv_rst=reset|(out1&out0);
assign fr_rst=reset|(out1&out0);
assign qinc=out1;
assign qdec=out0;
always @(posedge ref or posedge fv_rst) begin
    if(fv_rst) out0<=0;
    else       out0<=1;
end
always @(posedge ref or posedge fr_rst) begin
    if(fv_rst) out1<=0;
    else       out1<=1;
end
endmodule

// ...........................................cp cp cp...................

`include "discipline.vams"
`timescale 10ps/1ps
module cp(pout,nout,inc,dec)
input inc,dec;
output pout,nout;
electrical pout,nout;
parameter real cur=1m;
real out;
analog begin
    @(initial_step)
     out=0.0;
       if(dec&&!inc)
       out=~cur;
       else if(!dec&&inc)
           out=cur;
       else out=0;
       I(pout,nout)<+transition(out,0.0,10n,10n);
endmodule
// ...............................capacitor capacitor capacitor..........
`include "discipline.vams"
`timescale 10ps/1ps
module capacitor(p,n);
 inout p,n;
 electrical p,n;
 parameter real c=0 from [0:inf);
 analog
    I(p,n) <+ ddt(c*V(p,n));
endmodule
// ...............................resistr resister resister..........
`include "discipline.vams"
`timescale 10ps/1ps
module resister(p,n);
 inout p,n;
 electrical p,n;
 parameter real r=0 from [0:inf);
 analog
    V(p,n) <+ r*I(p,n);
endmodule
// ...............................vco vco vco...................... 
`include "discipline.vams"
`timescale 10ps/1ps
module vco(out,ps,ns)
parameter real fo=100k; //hz
parameter real kvco=10k;//hz\v
parameter real rin=100k from (0:inf);
output out;
input ps,ns;
electrical ps,ns;
logic out;
real vin;

initial out=0;
analog begin
vin=V(ps,ns);
#(0.5e9/(f0+kvco*vin)) out=~out;
end
analog I(ps,ns)<+V(ps,ns)/rin;
endmodule

// ............................................fd fd fd ...................
module fd(out,clk,reset);
input clk,reset
output out;
reg q,
reg [3:0] i;
always @(posedge clk or negedge reset) begin
    if(reset)
        i<=0;
    else if(i==8) i<=0;
    else    i<=i+1;
end

always @(posedge clk or negedge reset) begin
    if(reset)
        q<=0;
    else if(i==8)
       q<=~q;
    else   q<=q;
end
assign out=q&~reset;
endmodule